Click a gate button to add · Wire tool: click output then input port · Select: drag to move
📥 Inputs
Add INPUT gates to see controls here
📤 Outputs
Add OUTPUT gates to see values here
ℹ Circuit Info
Gates: 0
Wires: 0
CLK steps: 0
📊 Truth Table — Auto-generated from Circuit
Build a circuit in the Circuit Builder tab and click "Truth Table" or switch to this tab. The table is generated from your current INPUT/OUTPUT gates.
🔢 Manual Entry
Enter a Boolean expression to generate its truth table. Supports . for AND, + for OR, ~!A' for NOT:
🧠 Boolean Expression Solver
AND:AND&·. | OR:OR|+ | NOT:NOT~!A' | XOR:XOR^ | NANDNORXNOR
Variables: single letters A–Z. Parentheses supported. Examples:(A+B).CA'B + AB'NOT A AND (B OR C)A XOR B
🟦 Karnaugh Map
Click cells to toggle 0/1
📐 Simplified Expression
Click cells then press Simplify →
K-Map rules:
Group 1s in powers of 2 (1, 2, 4, 8, 16)
Groups wrap around edges
Largest groups → fewest literals
Each 1 must be in at least one group
Click any prebuilt circuit to load it instantly into the Circuit Builder.
➕
Half Adder
Adds two 1-bit numbers. Produces Sum (XOR) and Carry (AND).
2 inputs · 2 outputs
🔢
Full Adder
Adds three 1-bit inputs (A, B, Cin). Produces Sum and Carry-out.
3 inputs · 2 outputs
🔀
2-to-1 Multiplexer
Selects between inputs I0 and I1 using a selector S.
3 inputs · 1 output
🔒
SR Latch (NOR)
Basic memory cell using cross-coupled NOR gates.
2 inputs · 2 outputs
⊕
XOR from NAND
Implements XOR using only NAND gates (universal gate demo).
2 inputs · 1 output
📡
2-to-4 Decoder
Decodes 2-bit input into one of 4 active-high outputs.
2 inputs · 4 outputs
🔢 Counters
🔼
3-bit Up Counter (D FF)
Asynchronous ripple UP counter. Q̄→D toggle feedback on each FF. FF1.CLK = FF0.Q̄, FF2.CLK = FF1.Q̄ — counts 000→001→…→111→000.
CLK input · Q0 Q1 Q2 outputs
🔼
3-bit Up Counter (JK FF)
Synchronous counter. J=K=1 for FF0; J=K=Q0 for FF1; J=K=Q0·Q1 for FF2.
CLK input · Q0 Q1 Q2 outputs
↔ Shift Registers (D FF)
➡
SISO — Serial In Serial Out
3-bit shift register. Data enters one bit per CLK on SI and exits from the last FF (SO) after 3 clocks.
SI · CLK · SO
⭐
SIPO — Serial In Parallel Out
Bits shift in serially. After 3 CLKs all Q0/Q1/Q2 are available simultaneously (like 74HC164).
SI · CLK · Q0 Q1 Q2
📥
PISO — Parallel In Serial Out
LOAD=1 latches P0/P1/P2 into FFs simultaneously. LOAD=0 shifts Q2 out serially each CLK.
P0 P1 P2 · LOAD · CLK · SO
📦
PIPO — Parallel In Parallel Out
All 3 input bits P0/P1/P2 are latched to Q0/Q1/Q2 simultaneously on each CLK edge.
P0 P1 P2 · CLK · Q0 Q1 Q2
Interactive flip-flop simulators. Toggle inputs and click CLK to clock the flip-flop.
🔒 SR Flip-Flop
S (Set)
R (Reset)
Q
0
Q̄
1
S=1,R=0 → Set (Q=1) | S=0,R=1 → Reset (Q=0) S=0,R=0 → Hold | S=1,R=1 → Invalid
🔄 JK Flip-Flop
J
K
Q
0
Q̄
1
J=0,K=0 → Hold | J=1,K=0 → Set J=0,K=1 → Reset | J=1,K=1 → Toggle
📋 D Flip-Flop
D (Data)
Q
0
Q̄
1
On CLK rising edge: Q captures D Q⁺ = D (stores the data bit)
🔃 T Flip-Flop
T (Toggle)
Q
0
Q̄
1
T=0 → Hold | T=1 → Toggle Q Used in counters and frequency dividers
📉 Timing Diagram Visualizer
Toggle signal states and advance the clock to visualize waveforms across time.