FET Simulator

N-channel JFET

Shockley equation: I_D = I_DSS(1 − V_GS/V_P)². Tune I_DSS and V_P, click the transfer curve to set V_GS.

Enhancement NMOS (MOSFET)

Square-law: I_D = (k_n/2)(V_GS − V_T)². Tune k_n and V_T, click the transfer curve to set V_GS.

Quick experiments

• Find the threshold voltage. Raise Vgs from zero on the enhancement NMOS. Nothing flows until roughly Vth, then drain current climbs steeply. Threshold is defined at a small test current, not at full conduction.
• See why 3.3 V drive is not enough. A standard MOSFET specifies on-resistance at Vgs = 10 V. Drive it at 3.3 V and it sits part-way on, dissipating heat. A logic-level part is specified at 4.5 V and works from a microcontroller.
• Cross from ohmic into saturation. At low Vds the FET acts as a resistor and current rises with voltage — the switching region. Past Vgs − Vth the curve flattens and current depends only on the gate: the amplifying region.
• Contrast the JFET's depletion behaviour. The JFET conducts fully at Vgs = 0 and needs negative gate voltage to pinch off — the opposite of an enhancement MOSFET, which is off until driven.
• Turn on-resistance into heat. At 5 A through 50 mΩ the FET dissipates I²R = 1.25 W. Halving on-resistance halves the loss, which is why datasheets lead with that number.

Formula reference

Saturation-region drain current

$$I_D = \tfrac{1}{2} k \, (V_{GS} - V_{th})^{2}$$

Square law — current depends on gate overdrive, not on drain voltage.

Boundary between ohmic and saturation

$$V_{DS} = V_{GS} - V_{th}$$

Below this the FET is a resistor; above it, a current source.

Conduction loss in a switch

$$P_{cond} = I_D^{2} \, R_{DS(on)}$$

5 A through 50 mΩ gives 1.25 W.

Gate charge and drive current

$$I_{gate} = \frac{Q_g}{t_{switch}}$$

Switching 20 nC in 100 ns needs 200 mA of peak gate drive.

Common mistakes

• ✗Driving a standard MOSFET from 3.3 V or 5 V logic.

  If on-resistance is specified at Vgs = 10 V, logic-level drive leaves it partly on and it overheats. Use a logic-level FET or add a gate driver.

• ✗Treating threshold voltage as the turn-on point.

  Vth is measured at a few hundred microamps — barely conducting. Full conduction needs several volts of overdrive beyond it.

• ✗Leaving the gate floating.

  An insulated gate holds charge and can switch on from stray coupling. Fit a pull-down (for NMOS) so the FET is defined off whenever the driver is high-impedance.

• ✗Forgetting the body diode.

  Every power MOSFET has an intrinsic diode from source to drain. It conducts in reverse, so a single FET cannot block current in both directions — back-to-back pairs are needed.

• ✗Ignoring gate charge when switching fast.

  The gate is a capacitor. Driving 20 nC in 100 ns needs 200 mA of peak current; a weak driver slows the edge and the FET spends longer in its lossy linear region.

Frequently asked questions