Shift Register Simulator

One 4-bit register, four ways to get data in and out — SISO, SIPO, PISO and PIPO. Set the inputs, clock it, and watch each bit walk along the chain, with a running history of every edge so the shifting is something you can follow rather than infer.

Choose a mode, set inputs, and clock the register to watch data shift through four flip-flops.

FF3

FF2

FF1

FF0

Serial input

Output

Serial out:0

Four modes, one chain of flip-flops

A shift register is flip-flops in a line, each feeding the next. What changes between the four modes is only where data enters and where you read it. The names say it directly: SISO is serial in, serial out; SIPO takes bits in one at a time and presents all four at once; PISO loads all four and clocks them out one at a time; PIPO is a plain parallel register with no shifting at all.

SIPO and PISO are the two halves of serial communication

A SIPO turns a serial stream into parallel bits — the receiving end. A PISO does the reverse — the transmitting end. Put one of each at opposite ends of a wire pair and you have the core of SPI: a shift register on each side, clocked together, exchanging contents. This is also how a 74HC595 drives eight LEDs from three microcontroller pins.

Feed the output back and it becomes a counter

Wire the last stage back to the serial input and the register cycles a fixed pattern forever — a ring counter, one hot bit walking round. Feed back the inverted output instead and you get a Johnson counter, which gives 2n states from n flip-flops with only one bit changing at a time. Feed back an XOR of selected taps and you get an LFSR, the basis of pseudo-random sequence generators.

Learn more → Registers & Shift Registers — Learn

Quick experiments

Count the clocks it takes to fill the register. In SISO mode set the serial input to 1 and clock four times. The register reads 1111 and the first bit you fed in has just appeared at the serial output. An n-bit shift register delays a serial stream by exactly n clocks.
Push a single 1 through the chain. Set serial in to 1, clock once, then set it back to 0 and keep clocking. Watch the lone 1 walk 1000 → 0100 → 0010 → 0001 and then fall off the end. That travelling bit is a ring counter waiting for a feedback wire.
Serialise a parallel word. Switch to PISO, load 1011, then clock four times and watch the serial output produce those bits one at a time. This is exactly what happens on the MOSI line every time a microcontroller sends an SPI byte.
See why PIPO cannot shift. Select PIPO and try to clock. Nothing walks along — the mode captures all four bits at once and holds them. It is a storage register, not a shift register, and the widget disables the serial controls to say so.
Compare SIPO against SISO on the same data. Feed the same four bits into each. SISO gives you one bit per clock at the far end; SIPO gives you all four simultaneously after the fourth clock. Same chain of flip-flops, opposite trade between pin count and latency.

Formula reference

Clocks to fill or empty: $n_{clk} = n_{bits}$
A 4-bit register needs 4 edges to load serially.
Serial transfer time: $t = \frac{n_{bits}}{f_{clk}}$
8 bits at 1 MHz takes 8 µs.
Ring counter states: $\text{states} = n$
One hot bit circulating through n stages.
Johnson counter states: $\text{states} = 2n$
Inverted feedback doubles it — 4 stages give 8 states.
Maximum LFSR sequence: $\text{length} = 2^n - 1$
All states but one; the all-zero state is a lock-up.

Symbol	Meaning	Unit
$n_{bits}$	Stages in the register	—
$f_{clk}$	Shift clock frequency	Hz
$n$	Number of flip-flops in the ring	—

Common mistakes

Expecting parallel outputs to be valid mid-load in SIPO mode.
Until all n bits have been clocked in, the outputs are a mixture of new and stale data. Real parts solve this with a separate latch clock — the 74HC595's RCLK — so the outputs only update once the shift is complete.
Forgetting that a shift register delays a serial stream by n clocks.
The first bit in is the first bit out, but it arrives n edges later. In a pipeline that latency is real and has to be accounted for; treating the output as simultaneous with the input misaligns everything downstream.
Letting an LFSR reach the all-zeros state.
XOR feedback from an all-zero register produces zero forever — the sequence locks up and never restarts. Either seed it non-zero and never clear it, or use XNOR feedback, where the stuck state is all-ones instead.
Assuming a ring counter self-starts.
It has no way to reach the one-hot sequence on its own; power-on could leave it with several bits set, circulating an invalid pattern indefinitely. It needs an explicit preset or a self-correcting decode.
Clocking the shift and the load from the same edge without care.
If load and shift are both active at an edge the result depends on which wins internally. Make the mode select stable well before the edge, and treat load as a separate, mutually exclusive operation.

Frequently asked questions

What do SISO, SIPO, PISO and PIPO mean?

They describe how data enters and leaves. SISO is serial in serial out, SIPO takes bits in one at a time and presents them all at once, PISO loads all bits together and clocks them out one at a time, and PIPO loads and reads all bits in parallel with no shifting.

How many clock pulses does it take to load a shift register?

One per bit when loading serially, so a four-bit register needs four edges and an eight-bit register needs eight. That also means the register delays a serial stream by exactly its own length before the first bit reaches the far end.

What is the difference between a ring counter and a Johnson counter?

A ring counter feeds the last output back to the serial input, circulating one hot bit, and gives n states from n flip-flops. A Johnson counter feeds back the inverted output instead, giving 2n states with only one bit changing per clock.

Why do shift registers matter for serial communication?

A PISO at the transmitter turns a parallel word into a bit stream and a SIPO at the receiver turns it back. That pair, clocked together, is the core of SPI, and the same idea lets a 74HC595 drive eight outputs from three microcontroller pins.

Why must an LFSR never reach the all-zeros state?

XOR feedback from an all-zero register produces zero, so the sequence locks up and never restarts. Seed it with a non-zero value, or use XNOR feedback, where the stuck state becomes all-ones instead.