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Latches & Flip-Flops
SR latch, D latch, D/JK/T flip-flops, edge triggering, and excitation tables — the fundamental memory elements of sequential logic.
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Subject
Sequential logic fundamentals: latches, flip-flops, timing analysis, registers, counters, state machines, memory, and data conversion.
SR latch, D latch, D/JK/T flip-flops, edge triggering, and excitation tables — the fundamental memory elements of sequential logic.
Setup time, hold time, propagation delay, maximum clock frequency, and metastability — the rules every flip-flop must obey.
Parallel load, SISO/SIPO/PISO/PIPO shift registers, ring counter, Johnson counter, and LFSR — moving and storing multi-bit data.
Ripple counters, MOD-N truncation, propagation delay accumulation, and decode glitches — the simplest counters and their hidden timing problems.