Registers & Shift Registers

Digital Electronics · 13 min read

A single flip-flop stores one bit. Connect several together under a shared clock and you get a register — the basic word-storage unit inside every processor, memory chip, and serial interface.

Registers become intuitive only when you can see bits being captured and moved. Every section below has an interactive demo — press the clock button and watch what happens.

1. Parallel-Load Register

Four D flip-flops share a single clock line and an enable (EN) gate. On the active clock edge — when EN is HIGH — every flip-flop samples its D input at exactly the same instant. Before the edge, Q holds whatever it captured last.

Figure 1. 4-bit parallel-load register. Blue = D inputs (top), green = Q outputs (bottom), amber = shared CLK bus. On the rising clock edge all four flip-flops sample their D input simultaneously.

On the active clock edge, every flip-flop samples its D input at the same instant — the entire binary word is stored in a single clock cycle.

Try it — interactive capture

Toggle the D input bits, then press ↑ Clock Edge to capture them into Q. Watch the stored word update and the binary/decimal/hex interpretation below change.

D[3:0] — click bits to toggle

↓

Q registers — shared CLK

0FF3

0FF2

0FF1

0FF0

Q[3:0]0000₂= 0₁₀= 0x00

Before and after the clock edge

Figure 2. Timing diagram: D[3:0] = 1011 is presented to the register inputs. At the rising edge of CLK, Q[3:0] captures the value simultaneously. Between edges Q holds steady regardless of D changes.

2. Shift Register Types

Instead of loading all bits at once, a shift register moves data one bit per clock cycle. The four modes are named by how data enters and exits.

Type	Full name	Typical use
SISO	Serial In, Serial Out	Delay lines, serial links
SIPO	Serial In, Parallel Out	UART/SPI receivers, bus expansion
PISO	Parallel In, Serial Out	UART/SPI transmitters
PIPO	Parallel In, Parallel Out	Pipeline registers, CPU buffers

Figure 3. Four shift register configurations and their primary applications.

3. SISO — Serial In, Serial Out

Each clock edge pushes every bit one stage to the right. The oldest bit exits the last stage. Press Next Clock → below and watch 1011 load stage by stage.

Figure 4. SISO shift register: data enters at FF0, shifts right one position per clock, exits at FF3. Blue input wire, green output wire, gray inter-stage wires.

SISO step-through

Serial In:

A 4-bit SISO register needs 4 clock cycles to fully load — the first bit does not appear at the output until all stages have been shifted through.

4. SIPO — Serial In, Parallel Out

Same shift chain as SISO, but all four Q outputs are tapped simultaneously. After N clock cycles the full N-bit word appears at Q[3:0] at once — serial to parallel conversion.

Figure 5. SIPO shift register: data arrives bit-by-bit at SerIn, shifts through the chain, and all four Q outputs become available in parallel after 4 clock cycles. Used in UART receivers and SPI peripherals.

UART receiver: samples each data bit from the line, assembles a parallel byte.
SPI slave: shifts in the MOSI stream and presents a parallel byte to the MCU.

5. PISO — Parallel In, Serial Out

A control signal selects between two modes: LOAD (all D inputs captured in one cycle) and SHIFT (bits serialised out one per clock).

Figure 6. PISO shift register: parallel data is loaded in one clock, then shifted out serially. A LOAD/SHIFT̄ control line selects the mode. Used in UART transmitters and SPI controllers.

6. PIPO — Parallel In, Parallel Out

All bits in, all bits out — a pure pipeline register. It captures a snapshot of the data bus on the clock edge and holds it stable for one cycle while the next stage processes it.

Figure 7. PIPO register: same structure as the parallel-load register. Used as pipeline stage buffers in CPUs and between bus segments.

7. Ring Counter

Feed the last flip-flop’s Q output back to the first flip-flop’s D input and the register becomes a ring counter. A single 1 circulates continuously — one position per clock.

Figure 8. 4-bit ring counter: feedback from FF3.Q back to FF0.D. The single HIGH bit circulates: 1000 → 0100 → 0010 → 0001 → 1000 …

Watch the bit circulate

Ring counter — active bit circulates

Q[3:0]

Step 0

One-hot output — exactly one Q is HIGH at any time.
N flip-flops produce N unique states (vs 2N for a binary counter).
Used for simple sequencing, LED chasers, and one-hot state machines.

8. Johnson Counter

Feed back the complement of the last output — a “twisted ring” — and the counter produces 2N unique states from N flip-flops, with only one bit changing per clock (glitch-free decoded outputs).

Figure 9. 4-bit Johnson counter: Q̄3 feeds back to D0. The NOT bubble shows the inversion. The 8-state sequence is listed in the table.

State	Q3	Q2	Q1	Q0
0	0	0	0	0
1	1	0	0	0
2	1	1	0	0
3	1	1	1	0
4	1	1	1	1
5	0	1	1	1
6	0	0	1	1
7	0	0	0	1

Figure 10. 4-bit Johnson counter state sequence (8 unique states).

9. LFSR (Linear Feedback Shift Register)

XOR selected tap outputs and feed the result back to the input. With the right tap polynomial, an N-bit LFSR cycles through $2^N - 1$ states — a pseudo-random binary sequence (PRBS).

Figure 11. 4-bit LFSR with taps at FF3 and FF2 (polynomial x⁴ + x³ + 1). XOR of selected stages is fed back to the serial input. Used for CRC, data scrambling, and built-in self-test.

10. Real Applications

Register type	Real-world uses
Parallel register (PIPO)	CPU registers, pipeline buffers, bus latches
Shift register (SISO)	Delay lines, synchroniser chains
SIPO shift register	UART/SPI receivers, LED driver ICs
PISO shift register	UART/SPI transmitters, keyboard encoders
Ring counter	One-hot state machines, LED chasers, sequencing
Johnson counter	Phase generation, glitch-free decoders
LFSR	CRC, data scrambling, BIST, test patterns

Figure 12. Common register types and where they appear in real systems.