Common Base, Common Gate & Cascode — Worked Example

Designing a discrete cascode video amplifier

Scenario: A video signal chain needs Aᵥ = −50 V/V with bandwidth ≥ 50 MHz from a 50 Ω source. Use 2N3904 BJTs for both the CE and CB stages.

Device parameters: $C_{\mu} = 4\,\text{pF}$, $\beta = 200$, $V_A = 100\,\text{V}$, $V_{CC} = 12\,\text{V}$, $I_C = 5\,\text{mA}$.

1. Spec — Aᵥ = −50 V/V, bandwidth ≥ 50 MHz, Rₛ = 50 Ω.

   Compute transconductance and output resistance at 5 mA:

   $$g_m = \frac{I_C}{V_T} = \frac{5\,\text{mA}}{25\,\text{mV}} = 200\,\text{mA/V}$$
   $$r_o = \frac{V_A}{I_C} = \frac{100\,\text{V}}{5\,\text{mA}} = 20\,\text{k}\Omega$$

   For Aᵥ = −50, we need $R_C \approx 50 / g_m = 250\,\Omega$.

2. CE-alone bandwidth — fails the spec.

   With a single CE stage, the Miller effect multiplies Cμ by (1 + |Aᵥ|) = 51:

   $$C_{in,Miller} = C_{\mu} \cdot (1 + |A_v|) = 4\,\text{pF} \times 51 = 204\,\text{pF}$$
   $$f_{3dB,CE} = \frac{1}{2\pi \cdot R_S \cdot C_{in,Miller}} = \frac{1}{2\pi \times 50 \times 204 \times 10^{-12}} \approx 15.6\,\text{MHz}$$

   15.6 MHz < 50 MHz — fails the spec. A single CE stage cannot meet the bandwidth requirement with this gain.

3. Cascode design — stack a CB on top of the CE.

   The CB stage holds the CE collector at near-AC-ground, so Cμ is no longer multiplied:

   $$f_{3dB,cascode} = \frac{1}{2\pi \cdot R_S \cdot C_{\mu}} = \frac{1}{2\pi \times 50 \times 4 \times 10^{-12}} \approx 796\,\text{MHz}$$

   796 MHz ≫ 50 MHz — far exceeds the spec with ≈ 15× headroom before parasitic poles take over.

4. Bias design — both stages share Iᴄ = 5 mA.

   The lower CE (Q1) is biased with a standard voltage-divider (R₁, R₂). Set V_E,Q1 ≈ 1 V for stability: $R_E = V_E / I_C = 1 / 5\,\text{mA} = 200\,\Omega$.

   The upper CB (Q2) base is biased so that Q2's emitter sits about 0.7 V above Q1's collector. If Q1's collector sits at ≈ 5 V, then:

   $$V_{B,Q2} = V_{C,Q1} + V_{BE,Q2} \approx 5 + 0.7 = 5.7\,\text{V}$$

   Set the R_B3/R_B4 divider to deliver 5.7 V. With $V_{CC} = 12\,\text{V}$: use R_B3 = 6.8 kΩ, R_B4 = 5.6 kΩ (standard E24 values give ≈ 5.65 V).

5. Result — bandwidth and gain confirmed.
   $$A_v \approx -g_m \cdot R_C = -200\,\text{mA/V} \times 250\,\Omega = -50\,\text{V/V}\quad ✓$$
   $$f_{3dB} \approx 796\,\text{MHz}\quad \text{(15\times\ above 50 MHz spec)}\quad ✓$$

   The cascode delivers Aᵥ = −50 V/V at 5 mA with bandwidth headroom to ~800 MHz before parasitic poles (bond wires, package capacitance) take over. One extra transistor buys a 51× bandwidth win over the single CE stage.