Combinational Blocks

Digital Logic 101 · 12 min read

Why standard blocks

Real designs are not built from scattered NAND gates. The same handful of patterns — pick one of many, drive one of many, encode an active line, compare two numbers — show up so often that every standard cell library gives them their own block symbol with datasheet-grade timing.

Each block is just an SOP function with a tidy schematic and an IEC block-symbol shorthand. Internally they are gates; externally they are reusable lego.

1. Multiplexer (MUX)

n select bits choose 1 of 2ⁿ data inputs to drive a single output. A 4:1 MUX has 2 select bits S₁S₀ and 4 data inputs D₀..D₃.

Y = D_0 \cdot \overline{S_1}\,\overline{S_0} + D_1 \cdot \overline{S_1} S_0 + D_2 \cdot S_1 \overline{S_0} + D_3 \cdot S_1 S_0

Figure 1. Gate-level realisation of a 4:1 MUX. Two select buses S₁ and S₀ run vertically and tap into every AND's middle and bottom inputs. Inversion bubbles on the AND inputs encode the per-row decode: D0 row uses S₁′·S₀′, D1 uses S₁′·S₀, D2 uses S₁·S₀′, D3 uses S₁·S₀. Each AND's output drives one input of the 4-input OR that produces Y.

2 select bits → 4 data inputs (general: n → 2ⁿ).
Only one AND term is enabled at a time — the rest contribute 0.
Cascade: a 4:1 MUX from three 2:1 MUXes; an 8:1 from two 4:1s plus one 2:1.

2. Demultiplexer / Decoder

The inverse of a MUX: a 2-to-4 decoder takes 2 address bits A₁A₀ and asserts exactly one of 4 output lines Y₀..Y₃. With an enable input EN, the active output is gated:

Y_i = EN \cdot m_i(A_1, A_0)

Figure 2. Active-high 2-to-4 decoder. Three vertical buses A₁, A₀, EN tap into every AND. Inversion bubbles encode the per-row minterm (Y0 = EN·A₁′·A₀′ ; Y3 = EN·A₁·A₀). With EN held low all four outputs collapse to 0 — driving EN with a data line turns the decoder into a 1-to-4 demultiplexer.

n address bits → 2ⁿ outputs, exactly one active.
"Demultiplexer" = decoder reused as a router: data line on EN, address selects the channel.
Bigger decoders cascade from smaller ones (3-to-8 = 2× 2-to-4 + a top-level 1-to-2).

3. Encoder & priority encoder

A 2ⁿ-to-n encoder reverses the decoder: 2ⁿ input lines (only one assumed active) and n output lines giving its index in binary. The 4-to-2 encoder uses three OR gates — two for the binary index, one for a valid flag:

Y_1 = I_2 + I_3, \quad Y_0 = I_1 + I_3, \quad V = I_0 + I_1 + I_2 + I_3

Figure 3. 4-to-2 encoder gate diagram. Y₁ ORs the two inputs whose binary index has bit-1 set (I₂, I₃). Y₀ ORs those with bit-0 set (I₁, I₃). V ORs all four — high whenever any input is asserted.

Plain encoders break when more than one input is asserted — the OR-merge produces an index that doesn't correspond to any single input. The priority encoder resolves this by reporting the highest-index active input and uses V to distinguish "input 0" from "no input at all":

Inputs				Plain encoder		Priority encoder			Note
I₃	I₂	I₁	I₀	Y₁	Y₀	Y₁	Y₀	V
1	0	0	0	1	1	1	1	1
0	1	0	0	1	0	1	0	1
0	0	1	0	0	1	0	1	1
0	0	0	1	0	0	0	0	1
1	1	0	0	1	1	1	1	1	⚠ ambiguous index
0	1	1	0	1	1	1	0	1	⚠ ambiguous index
0	0	0	0	0	0	0	0	0	V=0 says "no input"

Figure 4. Behavior comparison. Plain encoder is correct only when at most one input is high; priority encoder always reports the winner.

4. Magnitude comparator

Two n-bit unsigned inputs A and B produce three exclusive flags. For equality, each bit position computes its own $eq_i = \overline{a_i \oplus b_i}$ (XNOR — true when that bit pair matches). A full match needs every bit to match, so the n bit-slice outputs feed an n-input AND (the big product symbol in the formula below):

F_{A=B} = \prod_{i=0}^{n-1} \overline{a_i \oplus b_i}

Magnitude takes the highest-index disagreeing bit. For a 4-bit comparator:

F_{A>B} = a_3\overline{b_3} + (a_3 \equiv b_3)\bigl[a_2\overline{b_2} + (a_2 \equiv b_2)(a_1\overline{b_1} + (a_1 \equiv b_1) a_0\overline{b_0})\bigr]

$F_{A<B}$ is symmetric (swap A and B). Most cells expose cascade inputs so wider comparators chain together: a 4-bit slice's outputs feed the next slice's cascade-in pins.

Figure 5. One bit-slice of a magnitude comparator. The XNOR detects equality on this bit; AND gates produce a > / < signal weighted by the higher slices being equal. Stack n slices and OR-priority them from MSB to LSB.

5. Block symbols and cascading

On schematics these blocks are usually drawn as IEC labelled rectangles — MUX as a trapezoid, decoder as a rectangle marked "DEC" or "1/n", comparator marked "COMP" with three output flags. The internal gates are abstracted away; the datasheet promises a propagation delay and you trust the cell.

Figure 6. IEC block shorthand. Schematics use these symbols once you trust the cell — no point redrawing the gate guts every time.

Building bigger blocks from smaller ones is the same pattern in every case: a top-level small block selects which lower-level slice is active. 8:1 MUX = two 4:1 MUXes feeding a 2:1 MUX; 3-to-8 decoder = a 1-to-2 decoder enabling one of two 2-to-4 decoders.