Logic Gates — worked example

Digital Logic 101 · Logic Gates · Example

Build a 3-input AND from NAND gates

Figure 1. 3-input AND from four 2-input NANDs. Stage 1 combines A and B into a NAND; stage 2 inverts that NAND back to AND; stage 3 ANDs the result with C via the same NAND-then-invert trick.

Stage 1 — NAND of A and B. Compute $P = \overline{A \cdot B}$ with one 2-input NAND.
Stage 2 — invert P to recover AND. Tie both inputs of a second NAND to $P$ ; the gate behaves as a NOT, so its output is $Q = \overline{P} = A \cdot B$ .
Stage 3 — NAND of Q and C. $R = \overline{Q \cdot C} = \overline{A \cdot B \cdot C}$ .
Stage 4 — invert R. A fourth NAND with both inputs tied to $R$ outputs $Y = \overline{R} = A \cdot B \cdot C$ . Done — four NANDs, no other gate types.

Verify with the 8-row truth table

A	B	C	A·B·C	Y
0	0	0	0	0
0	0	1	0	0
0	1	0	0	0
0	1	1	0	0
1	0	0	0	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Figure 2. Y agrees with A · B · C in every row, so the four-NAND network correctly implements 3-input AND.

The pattern NAND-then-NAND-as-NOT appears every time you want an AND from NANDs. Cascading

n

-input AND from 2-input NANDs takes

2(n - 1)

NAND gates total — two per AND-pair.

Try drawing this — and other circuits — in the Simulate stage.