Hazards & Glitches — worked example
Digital Logic 101 · Hazards & Glitches · Example
Setup
Build F = A·B + A'·C from elementary AND/OR/NOT cells. Every gate has the same propagation delay τ = 5 ns. We probe the most exposed corner of the truth table: B = C = 1 with A stepping 1 → 0 at t = 10 ns.
Boolean algebra collapses F at B=C=1 to F = A + A' = 1, so the output is supposed to stay at 1 across the edge. We'll see that timing makes it dip to 0 for one gate delay before recovering.
Step 1 — Identify the two paths
Trace each AND-gate output back to the changing input A:
- Top path (A·B): A directly into the AND. One gate from A to A·B.
- Bottom path (A'·C): A through an inverter, then into the AND. Two gates from A to A'·C.
The OR sits one gate further on. The two paths reconverge with a 1·τ delay difference — that asymmetry is the hazard.
Step 2 — Hand-simulate the timeline
Tabulate each signal's level at the milestone times. Edges propagate from A at t = 10 ns:
| Signal | t < 10 | t = 10 | t = 15 | t = 20 | t = 25 |
|---|---|---|---|---|---|
| A | 1 | ↓ 0 | 0 | 0 | 0 |
| A' (= NOT A) | 0 | 0 | ↑ 1 | 1 | 1 |
| A·B | 1 | 1 | ↓ 0 | 0 | 0 |
| A'·C | 0 | 0 | 0 | ↑ 1 | 1 |
| F | 1 | 1 | 1 | ↓ 0 | ↑ 1 |
- At t = 10 ns, A flips 1 → 0. A·B (top path, 1 gate) reacts after τ = 5 ns and falls at t = 15 ns. A' is still 0 at this instant — the inverter is also one delay behind.
- From t = 15 ns to t = 20 ns, both A·B and A'·C are 0. The OR sees 0 + 0 = 0, so F drops one delay later — at t = 20 ns the OR's output goes to 0.
- At t = 15 ns, A' rose to 1. The bottom AND (A'·C with C=1) can fire one more delay later, at t = 20 ns. So A'·C = 1 again at t = 20 ns.
- The OR then sees 0 + 1 = 1 and recovers at t = 25 ns. F is back at its steady-state value.
Net result: F = 0 from t = 20 ns to t = 25 ns — a 5-ns static-1 glitch.
Step 3 — Derive the consensus cover
The consensus theorem rewrites F without changing its function:
The extra term B·C is logically redundant — every minterm it covers is already covered by A·B or A'·C. But it is a hazard cover: when A toggles with B = C = 1, B·C is independently 1 the entire time. The OR now has a never-falling input, and F can never dip.
Step 4 — Hand-simulate the covered circuit
| Signal | t < 10 | t = 15 | t = 20 | t = 25 |
|---|---|---|---|---|
| A·B | 1 | 0 | 0 | 0 |
| A'·C | 0 | 0 | 1 | 1 |
| B·C (cover) | 1 | 1 | 1 | 1 |
| F = AB + A'C + BC | 1 | 1 | 1 | 1 |
B·C carries F across the gap. The cost is one extra AND gate and one extra OR input — usually trivial compared to the cost of debugging an intermittent glitch in real hardware.
How this generalises
- Find every K-map adjacency between two prime implicants that don't overlap. Each one is a potential static-1 hazard.
- Add a cover term for each gap — usually the consensus of the two adjacent groups.
- POS form has duals: static-0 hazards live between non-overlapping prime implicants on the 0-cells, and they're covered by extra maxterms.