Hazards & Glitches

1. Why glitches happen

Every gate takes time to switch — typically 1–10 ns for small CMOS cells. On a single input transition, two parallel paths through different gates rarely arrive at the output simultaneously. The faster path "un-asserts" while the slower path is still stale, and the output briefly takes the wrong value before settling back to the correct one. That brief excursion is a glitch; the underlying race is a hazard.

Figure 1. Two paths converge on the output. If they have different total delays, F glitches during input transitions even though the boolean function is constant.

Boolean algebra says F has a defined value for every input combination. Timing says the output passes through intermediate values during transitions. Hazard analysis closes the gap between the two views.

2. Static-1 hazard

A static-1 hazard is when the output is supposed to stay at 1 across an input change but transiently dips to 0. Mirror image: a static-0 hazard dips up to 1. The textbook example uses three inputs:

F = A \cdot B + \overline{A} \cdot C

Hold B = C = 1 and toggle A: 1 → 0. Both before and after the edge, F should be 1 (with B=C=1 the function reduces to F = A + A' = 1). But with finite gate delay, AB falls before A'C rises, and the OR briefly sees both inputs at 0:

Figure 2. Static-1 race on F = AB + A'C. Top path: AB falls one delay after A. Bottom path: A'C rises two delays after A (NOT then AND). The OR sits at 0 from t=2τ to t=3τ — that's the glitch.

3. The K-map tells you exactly where hazards live

Plot F = AB + A'C on a 3-variable K-map. The two prime implicants AB and A'C cover adjacent 1-cells but the groups don't share any cell. The transition (A=1,B=1,C=1) → (A=0,B=1,C=1) crosses the gap between the two groups — and that's precisely where the hazard occurs:

Figure 3. K-map for F = AB + A'C. Two groups (AB on the right, A'C on top) cover adjacent 1-cells with no overlap. The dashed arrow marks the input transition that races. The B·C consensus term (dotted oval) covers the gap and eliminates the hazard.

Static-1 hazards live exactly at K-map adjacencies between prime-implicant groups that don't overlap. Cover the gap with an extra (redundant) prime implicant — usually the consensus term — and the hazard disappears.

4. Covering the hazard with the consensus term

The consensus theorem tells us that

A \cdot B + \overline{A} \cdot C = A \cdot B + \overline{A} \cdot C + B \cdot C

Adding B·C is logically redundant — the function is the same. But it bridges the K-map gap: when A toggles with B=C=1, the BC term is independently 1 the whole time, so the OR has at least one input asserted and F never dips. The price is one extra AND gate (and one extra OR input).

5. Static-0 and dynamic hazards

Static-0 hazards are the dual: F should stay at 0 but blips up to 1. They live in the POS form at adjacent 0-cells and are covered by adding redundant maxterms. Dynamic hazards are bigger trouble — the output makesmultiple transitions on a single input change (e.g. 0 → 1 → 0 → 1) because three or more parallel paths with different delays all race. Dynamic hazards usually mean a deeper circuit needs restructuring, not just a cover term.

Figure 4. Three hazard shapes on a single input transition. Static-1 dips, static-0 spikes, dynamic ripples. All three vanish if the design is glitch-free or downstream logic is clocked safely.

6. When does this actually matter?

Asynchronous paths. A glitch into a flip-flop's clock, async-set, or async-reset input can latch a wrong value or trigger a false reset. These are the failures that survive simulation and bite in the lab.
Clocked logic. Combinational glitches between two flip-flops are usually fine — the next clock edge samples the settled value, and the glitch never reaches a register.
Edge-triggered counters / state machines.Watch any signal that drives a clock or async control. Pure datapath logic generally tolerates glitches.