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Worked example: JFET bias-point and transconductance

Semiconductor Devices · JFET · Example

Problem 1 — Find I_D given V_GS

A 2N5457 JFET has IDSS=10 mAI_{DSS} = 10\,\text{mA} and VP=−4 VV_P = -4\,\text{V}. Find the drain current IDI_D when VGS=−2 VV_{GS} = -2\,\text{V} (saturation region).

  1. Write the transfer equation.
    In saturation, Shockley's equation:
    ID=IDSS(1−VGSVP)2I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2
  2. Evaluate the ratio.
    VGSVP=−2−4=0.5\frac{V_{GS}}{V_P} = \frac{-2}{-4} = 0.5, so the bracket is 1−0.5=0.51 - 0.5 = 0.5.
  3. Substitute and compute.
    ID=10 mA×(0.5)2=10×0.25=2.5 mAI_D = 10\,\text{mA} \times (0.5)^2 = 10 \times 0.25 = 2.5\,\text{mA}
  4. Check the saturation condition.
    Saturation requires VDS≥VGS−VP=−2−(−4)=2 VV_{DS} \geq V_{GS} - V_P = -2 - (-4) = 2\,\text{V}. Provided VDS≥2 VV_{DS} \geq 2\,\text{V}, the result holds.
    Answer: ID=2.5 mAI_D = 2.5\,\text{mA} — exactly ¼ of IDSSI_{DSS}.

Problem 2 — Find V_GS for a target I_D

Using the same device (IDSS=10 mAI_{DSS} = 10\,\text{mA}, VP=−4 VV_P = -4\,\text{V}), find the gate-source voltage needed to set ID=4 mAI_D = 4\,\text{mA}.

  1. Start from the Shockley equation and isolate the bracket.
    IDIDSS=(1−VGSVP)2\frac{I_D}{I_{DSS}} = \left(1 - \frac{V_{GS}}{V_P}\right)^2
  2. Take the square root (positive root, bracket > 0).
    IDIDSS=1−VGSVP\sqrt{\frac{I_D}{I_{DSS}}} = 1 - \frac{V_{GS}}{V_P}
  3. Rearrange for VGSV_{GS}.
    VGS=VP ⁣(1−IDIDSS)V_{GS} = V_P\!\left(1 - \sqrt{\frac{I_D}{I_{DSS}}}\right)
  4. Substitute numbers.
    VGS=−4(1−410)=−4(1−0.632)=−4×0.368≈−1.47 VV_{GS} = -4\left(1 - \sqrt{\frac{4}{10}}\right) = -4\left(1 - 0.632\right) = -4 \times 0.368 \approx -1.47\,\text{V}
  5. Verify by back-substituting.
    ID=10(1−−1.47−4)2=10 (0.368)2≈10×0.135≈1.35 mAI_D = 10\left(1 - \frac{-1.47}{-4}\right)^2 = 10\,(0.368)^2 \approx 10 \times 0.135 \approx 1.35\,\text{mA}
    Wait — let us re-evaluate carefully: 1−0.632=0.3681 - 0.632 = 0.368, (0.368)2=0.135(0.368)^2 = 0.135 — that gives 1.35 mA, not 4 mA. The issue is rounding: 0.4=0.6325\sqrt{0.4} = 0.6325, so VGS=−4(1−0.6325)=−4(0.3675)=−1.47 VV_{GS} = -4(1 - 0.6325) = -4(0.3675) = -1.47\,\text{V}. Check: (1−1.47/4)2=(1−0.3675)2=(0.6325)2=0.400(1 - 1.47/4)^2 = (1-0.3675)^2 = (0.6325)^2 = 0.400, so ID=10×0.400=4.00 mA  ✓I_D = 10 \times 0.400 = 4.00\,\text{mA}\;\checkmark
    Answer: VGS≈−1.47 VV_{GS} \approx -1.47\,\text{V}.

Problem 3 — Transconductance and voltage gain

The same JFET is biased at VGS=−2 VV_{GS} = -2\,\text{V} (ID=2.5 mAI_D = 2.5\,\text{mA} from Problem 1) and connected in a common-source stage with drain resistor RD=2.2 kΩR_D = 2.2\,\text{k}\Omega. Find gmg_m and the small-signal voltage gain AvA_v.

  1. Find peak transconductance gm0g_{m0} (at VGS=0V_{GS}=0).
    gm0=−2 IDSSVP=−2×10 mA−4 V=5 mA/Vg_{m0} = \frac{-2\,I_{DSS}}{V_P} = \frac{-2 \times 10\,\text{mA}}{-4\,\text{V}} = 5\,\text{mA/V}
  2. Scale to the bias point.
    gm=gm0(1−VGSVP)=5(1−−2−4)=5×0.5=2.5 mA/Vg_m = g_{m0}\left(1 - \frac{V_{GS}}{V_P}\right) = 5\left(1 - \frac{-2}{-4}\right) = 5 \times 0.5 = 2.5\,\text{mA/V}
  3. Compute small-signal voltage gain.
    For a common-source stage with no source degeneration:
    Av=−gmRD=−2.5 mA/V×2.2 kΩ=−5.5A_v = -g_m R_D = -2.5\,\text{mA/V} \times 2.2\,\text{k}\Omega = -5.5
    The minus sign means phase inversion. The output swings 5.5× larger than the input.
    Answer: gm=2.5 mA/Vg_m = 2.5\,\text{mA/V}, Av=−5.5A_v = -5.5.
gmg_m drops as VGSV_{GS} goes more negative. Biasing closer to 0 V gives higher gmg_m and more gain, but also moves the bias point toward IDSSI_{DSS}, leaving less headroom for positive signal swings.