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Metal-Oxide-Semiconductor FET (MOSFET)

Semiconductor Devices · MOSFET · Learn

Gate (metal/poly)SiO₂ (insulator)p-substrate(acceptors, holes)n⁺sourcen⁺drainn-channel (inversion layer — forms when VGS > VT)GSDB(body)← channel length L →
Figure 1. Enhancement NMOS cross-section. The n-channel forms at the Si–SiO₂ interface when V_GS exceeds the threshold voltage V_T.

The MOSFET has four terminals: Gate (G), Drain (D), Source (S), and Body/Bulk (B). The gate is separated from the semiconductor by a thin silicon-dioxide insulator — so gate current is essentially zero at DC. This distinguishes MOSFET from both BJT (base current required) and JFET (gate diode leakage).

In the enhancement NMOS shown above, the substrate is p-type. Source and drain are n⁺-doped. With VGS = 0 there is no conduction path. When VGS exceeds the threshold voltage VT, the electric field repels holes and attracts electrons to the surface, forming an n-type inversion layer (the channel) that connects S to D.

GDSE-NMOSGDSE-PMOSGDSD-NMOSGDSD-PMOS
Figure 2. MOSFET circuit symbols. Broken body bar = enhancement mode (no built-in channel). Solid body bar = depletion mode. Arrow direction: inward (NMOS, n-channel); outward (PMOS, p-channel). Body is shown tied to source.

MOSFETs come in four varieties. The most common in digital and switching circuits is the enhancement NMOS (E-NMOS). Enhancement-mode devices need VGS to exceed VT to conduct. Depletion-mode devices have a built-in channel and can be operated with VGS = 0 or even below zero.

  • E-NMOS — VT > 0; OFF at VGS = 0
  • E-PMOS — VT < 0; OFF at VGS = 0 (needs VGS < VT)
  • D-NMOS — VT < 0; ON at VGS = 0
  • D-PMOS — VT > 0; ON at VGS = 0
01234560481216VGS (V)ID (mA)VT= 2 VOFF (ID=0)(4 V, 4 mA)kn=2 mA/V²VT=2 V
Figure 3. Transfer characteristic of an E-NMOS (kn = 2 mA/V², VT = 2 V). No current flows below VT; above VT the drain current rises as the square of the overdrive voltage (VGS − VT).

In the saturation region the MOSFET behaves as a voltage-controlled current source:

ID=kn2(VGS−VT)2VDS≥VGS−VT>0I_D = \frac{k_n}{2}(V_{GS} - V_T)^2 \qquad V_{DS} \geq V_{GS} - V_T > 0
kn=μnCoxWLk_n = \mu_n C_{ox} \frac{W}{L}

In the triode (linear) region both ends of the channel are open:

ID=kn ⁣[(VGS−VT)VDS−VDS22]0<VDS<VGS−VTI_D = k_n\!\left[(V_{GS}-V_T)V_{DS} - \frac{V_{DS}^2}{2}\right] \qquad 0 < V_{DS} < V_{GS} - V_T

The transconductance in saturation:

gm=kn(VGS−VT)=2knIDg_m = k_n(V_{GS} - V_T) = \sqrt{2 k_n I_D}
0246810048121620VDS (V)ID (mA)VGS=3VVGS=4VVGS=5VVGS=6VTriodeSaturation
Figure 4. Output curves for an E-NMOS (kn = 2 mA/V², VT = 2 V). The dashed boundary marks VDS = VGS − VT (pinch-off locus). Left of the boundary: triode region. Right: saturation.

The pinch-off locus (dashed line) separates the two regions. In saturation the curves are nearly flat — ID depends mainly on VGS, not VDS. In triode the MOSFET acts as a voltage-controlled resistor: for small VDS, rDS≈1/[kn(VGS−VT)]r_{DS} \approx 1/[k_n(V_{GS}-V_T)].

VDDRDVoutVinVin < VTChannel OFFID = 0Vout = VDD (HIGH)Vin > VTChannel ONID = (VDD−Vout)/RDVout ≈ 0 (LOW)
Figure 5. NMOS common-source inverter. When V_in is below V_T the transistor is OFF — no current flows and V_out is pulled to V_DD. When V_in exceeds V_T the channel forms, current flows through R_D, and V_out drops toward 0 V.

The NMOS inverter demonstrates the two digital states:

  • OFF: VGS < VT → ID = 0, no voltage drop across RD, Vout = VDD (logic HIGH).
  • ON: VGS > VT → channel conducts, ID rises, VDD divides between RD and the MOSFET, Vout falls toward 0 V (logic LOW).

This action is the basis of CMOS inverters, NAND gates, and every other standard digital logic cell.

The MOSFET gate draws no DC current (insulated oxide), making it ideal for high-density CMOS. Unlike the JFET, enhancement-mode MOSFETs are fully OFF at VGS = 0 — no need to reverse-bias the gate to cut off the channel.

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