Timing Analyzer

Drag setup time, hold time and propagation delay and watch the timing diagram respond. The setup and hold windows are drawn around the clock edge, violations are flagged as they happen, and the maximum clock frequency updates with every change.

Setup Time t_su: 5 nsHold Time t_h: 2 nsPropagation Delay t_pd: 10 nsD transition (before clock edge): 15 ns

Timing Rules— live status updates as you move sliders

Setup timedata_offset ≥ t_su (5 ns)

D transitions 15 ns before edge — 10 ns margin

✓ PASS

Hold timeD stable for ≥ t_h (2 ns) after edge

D doesn't change after the edge — hold margin = ∞

✓ PASS

Max frequencyf_clk ≤ f_max = 1 / (t_pd + t_su)

f_max = 1 / (10 + 5) ns = 66.7 MHz | T_min = 15 ns

✓ PASS

Maximum Clock Frequency

\small f_{max} = \tfrac{1}{t_{pd}+t_{su}} = \tfrac{1}{10+5} = \tfrac{1}{15\,\text{ns}}

66.7 MHz

Minimum Clock Period

\small T_{min} = t_{pd} + t_{su} = 10 + 5 = 15\;\text{ns}

Pipeline: T_clk ≥ t_pd(FF1) + t_comb + t_su(FF2)

Forbidden (setup) Forbidden (hold) Safe region Propagation delay

A window around the edge, not a moment

A flip-flop does not sample its input at an infinitely thin instant. It needs the data steady for t_su before the clock edge and held for t_h after it. Together those form a forbidden window: change the data inside it and the device may not resolve cleanly. Everything else in synchronous design exists to keep transitions out of that window.

Why setup and propagation set the speed limit

Between two flip-flops, a clock edge launches data out of the first after t_pd, and it must arrive at the second at least t_su before the following edge. So one clock period must be at least t_pd + t_su, plus whatever combinational logic sits between them. With the defaults above — 10 ns propagation and 5 ns setup — the floor is 15 ns, which is why the readout says about 66.7 MHz.

Hold violations do not care how slow you run

A setup violation is fixed by slowing the clock down — more time between edges. A hold violation is not, because it is about data arriving too early after an edge, which is unchanged by the clock period. Hold failures are a routing and delay problem, usually fixed by adding delay on the fast path, and they are the reason a design can fail at every frequency including very low ones.

Metastability, when the window is missed

Violate the window and the output can sit between logic levels for an unbounded time before settling to a random one. It cannot be designed out entirely for genuinely asynchronous inputs — a button, another clock domain — only made improbable, by passing the signal through two flip-flops in series so the first has a full clock period to resolve.

Learn more → Timing Analysis — Learn

Quick experiments

Walk the data into a setup violation. Drag the D transition closer to the clock edge until it crosses the setup boundary. The diagram flags it the moment the data changes less than t_su before the edge — the violation is geometric, and you can see exactly where it starts.
Prove hold violations survive a slower clock. Create a hold violation by moving the data transition just after the edge. Now imagine stretching the clock period: the overlap does not change. Hold is measured from the edge, not from the period, which is why slowing down never fixes it.
Trade setup time against maximum frequency. Take setup from 5 ns to 15 ns with propagation fixed at 10 ns. Maximum frequency falls from about 66.7 MHz to 40 MHz. The two numbers add before they are inverted, so a slow input stage costs exactly as much as slow logic.
Find the propagation delay that halves your clock. Leave setup at 5 ns and push propagation from 10 ns to 25 ns. The period floor goes 15 ns to 30 ns and f_max halves. This is what happens when you add a slow buffer in a feedback path.
Shrink the forbidden window. Set both setup and hold to their minimum. The shaded region around the edge narrows and almost any data placement passes — the ideal device that real silicon approximates but never reaches.

Formula reference

Minimum clock period: $T_{min} = t_{pd} + t_{logic} + t_{su}$
Launch, travel, and arrive in time to be sampled.
Maximum clock frequency: $f_{max} = \frac{1}{t_{pd} + t_{su}}$
With no logic between stages. 10 ns + 5 ns gives about 66.7 MHz.
Setup slack: $\text{slack}_{su} = T_{clk} - (t_{pd} + t_{logic} + t_{su})$
Negative means the path is too slow. Slowing the clock helps.
Hold slack: $\text{slack}_{h} = t_{pd} + t_{logic} - t_{h}$
No T_clk term — which is why a slower clock cannot fix a hold failure.
Setup and hold window: $t_{window} = t_{su} + t_{h}$
The span around the edge where data must not move.

Symbol	Meaning	Unit
$t_{su}$	Setup — data stable before the edge	ns
$t_{h}$	Hold — data stable after the edge	ns
$t_{pd}$	Clock-to-output propagation delay	ns
$T_{clk}$	Clock period	ns

Common mistakes

Trying to fix a hold violation by slowing the clock.
It will not work. Hold is measured from the clock edge, so the period does not appear in the hold slack equation at all. The fix is to add delay on the offending data path or rebalance the clock tree.
Quoting f_max from propagation delay alone.
Setup time is part of the same period. A device with 10 ns propagation and 5 ns setup runs at 66.7 MHz, not 100 MHz — and any combinational logic between the stages comes out of the same budget.
Feeding an asynchronous input straight into logic.
A button press or a signal from another clock domain will eventually change inside the setup-hold window, and the resulting metastable output can propagate to several places that then disagree. Synchronise with two flip-flops in series first.
Assuming setup and hold times are symmetric.
They rarely are, and hold is sometimes specified as zero or even negative. Read both from the datasheet at the actual supply voltage and temperature rather than assuming a window centred on the edge.
Ignoring clock skew between the launching and capturing flip-flops.
If the capture clock arrives late, setup gets easier and hold gets harder; early is the reverse. Skew adds directly to the slack equations, and on a large design it is often the difference between passing and failing.

Frequently asked questions

What are setup time and hold time?

Setup time is how long the data must be stable before the clock edge; hold time is how long it must stay stable after. Together they form a window around the edge in which the data must not change, or the flip-flop may not resolve to a valid level.

Why does slowing the clock not fix a hold violation?

Hold time is measured from the clock edge, not from the clock period, so the period does not appear in the hold slack equation at all. Making the clock slower changes nothing. Hold failures are fixed by adding delay on the fast data path or by rebalancing the clock tree.

How do I calculate maximum clock frequency?

Add the clock-to-output propagation delay, any combinational logic delay between the stages, and the setup time of the receiving flip-flop, then take the reciprocal. With 10 nanoseconds propagation and 5 nanoseconds setup and no logic between, that is 15 nanoseconds, or about 66.7 megahertz.

What is metastability?

If the data changes inside the setup-hold window, the output can hang between logic levels for an unbounded time before settling to an unpredictable value. It cannot be eliminated for genuinely asynchronous inputs, only made very improbable by passing the signal through two flip-flops in series.

What is timing slack?

The margin by which a path passes. Setup slack is the clock period minus the total path delay including setup; hold slack is the path delay minus the required hold time. Negative slack means the constraint is violated, and the number tells you by how much.