Timing Analysis

Every flip-flop needs data to be stable around the clock edge — not just at the exact instant, but for a small window before and after. Violate that window and the output becomes unpredictable.

Why? A flip-flop is a physical circuit that needs time to reliably decide whether the input is 0 or 1. If the input is still changing when the flip-flop tries to sample it, the internal voltage can get stuck between the two valid levels — a dangerous condition called metastability.

1. Propagation Delay ( $t_{pd}$ )

After the clock edge captures D, Q does not change instantly — it takes a small delay for the signal to propagate through the flip-flop's internal gates.

Figure 1. Propagation delay: the blue arrow shows the time from the rising clock edge until Q settles to its new value.

$t_{pd}$ is the clock-to-Q delay — typically 5–15 ns for standard logic families.
A 74HC74 has $t_{pd} \approx 15\,\text{ns}$ .

Worked example

If $t_{pd} = 10\,\text{ns}$ and the clock period is 100 ns, Q settles just 10 ns after the edge — leaving 90 ns of margin before the next edge.

2. Setup Time ( $t_{su}$ )

Data must be stable before the clock edge arrives — the flip-flop needs time to "read" the input before it latches.

Figure 2. Setup time: the red-shaded forbidden region before the clock edge. D must be stable before this window ends. Green region = safe.

D must not change during $[\text{edge} - t_{su},\;\text{edge}]$ .
Typical: $t_{su} \approx 5\,\text{ns}$ for a 74HC74.

Setup time defines the deadline: data must arrive and settle before the clock edge by at least $t_{su}$ .

What happens when setup time is violated?

Figure 3. Setup violation: D changes inside the red forbidden region. Q enters a metastable state — it oscillates before settling to an unpredictable value.

When D changes too close to the clock edge, the flip-flop cannot reliably resolve whether D was 0 or 1 — the output wobbles before eventually settling to a random value.

3. Hold Time ( $t_h$ )

Data must also remain stable after the clock edge — the flip-flop needs a brief moment to finish latching the value.

Figure 4. Hold time: the amber-shaded forbidden region after the clock edge. D must remain stable until this window ends.

D must not change during $[\text{edge},\;\text{edge} + t_h]$ .
Typical: $t_h \approx 2\,\text{ns}$ . Many modern FFs have $t_h \approx 0$ , but never assume this without checking the datasheet.

Hold violation

Figure 5. Hold violation: D changes immediately after the clock edge, inside the amber window. Q becomes metastable.

4. Maximum Clock Frequency

The clock period must be long enough for Q to settle (propagation delay) and for the next flip-flop to see stable data (setup time).

f_{max} = \frac{1}{t_{pd} + t_{su}}

Worked example

$t_{pd} = 10\,\text{ns}$ , $t_{su} = 5\,\text{ns}$ :

f_{max} = \frac{1}{10 + 5} = \frac{1}{15\,\text{ns}} = 66.7\,\text{MHz}

Pipeline timing

When combinational logic sits between two flip-flops:

T_{clk,min} = t_{pd}(\text{FF1}) + t_{comb} + t_{su}(\text{FF2})

Example: FF1 ( $t_{pd}=8$ ns) → adder ( $t_{comb}=20$ ns) → FF2 ( $t_{su}=5$ ns):

$T_{min} = 8 + 20 + 5 = 33\,\text{ns}$ → $f_{max} = 30.3\,\text{MHz}$

5. Metastability — Why Timing Matters Physically

A flip-flop is built from cross-coupled gates that have two stable states (0 and 1). When setup or hold time is violated, the internal voltage gets stuck between these states — like a ball balanced on the top of a hill.

Eventually it will fall to one side, but how long it takes is unpredictable — it could be nanoseconds or microseconds. During this time, the output is neither a valid 0 nor a valid 1, and downstream logic may interpret it differently, causing cascading errors.

Metastability can cause intermittent, hard-to-debug failures in digital systems.
Synchronizer circuits (two flip-flops in series) reduce the probability but never eliminate it entirely.
This is why every signal crossing between clock domains must pass through a synchronizer.