Common-Emitter & Common-Source Amplifier

1. The voltage-amplifier role

👉 Simple analogy — see-saw / lever

• Input side goes up → output side goes down (inverting).
• The leverage (gain magnitude) depends on $R_C$ and $g_m$ — bigger lever, bigger swing.
• A small wiggle at the base produces a big inverted wiggle at the output.

1.1 What it does

Takes a small input voltage swing at the base (or gate) and produces a much larger,inverted voltage swing at the collector (or drain).

1.2 The “voltage amplifier” role

High gain, inverting, moderate input impedance, moderate output impedance. The workhorse of analog signal-chain design.

1.3 Why inverting?

When $V_{BE}$ (or $V_{GS}$) goes UP, $I_C$ (or $I_D$) goes UP. More current drops more voltage across $R_C$, so $V_C = V_{CC} - I_C R_C$ goes DOWN. The output is 180° out of phase with the input.

2. Small-signal gain derivation

👉 Simple analogy — water taps in parallel

• The transistor's current source is like a tap pouring $g_m \cdot v_{be}$ amperes into a bucket.
• $R_C$, $r_o$, and $R_L$ are three drains on the bucket.
• Voltage rise = current ÷ total drain rate = current × (parallel resistance). Bigger drains → smaller gain.

2.1 Strip away DC

Replace $V_{CC}$ with AC ground — DC supplies have zero impedance to signals. Any bypass capacitor also becomes a short at signal frequencies.

2.2 Plug in the model

Replace the transistor with its hybrid-π (BJT) or FET small-signal model. With the bypass cap present, $R_E$ (or $R_S$) shorts to AC ground.

2.3 Apply Ohm's law

The controlled current $g_m v_{be}$ flows through $R_C \| r_o \| R_L$. The output voltage is:

Where:

• $g_m$ is the transconductance from Topic 1 (typically 40–100 mA/V at $I_C \approx 1\,\text{mA}$).
• $R_C \| r_o \| R_L$ is the parallel combination of all resistances at the output node.
• The minus sign means inverting — $V_{out}$ is 180° out of phase with $V_{in}$.

3. Signal swing along the load line

Now that we know the gain, let's see what the signal actually does on the output characteristic family from Topic 1.

3.1 The Q-point is the rest position

With no input signal, the operating point sits at the Q-point — $V_{CE} \approx V_{CC}/2$, on the chosen $I_B$ curve. Both halves of the swing have equal headroom.

3.2 The signal slides along the load line

Apply a small AC $v_{in}$. The base current swings from $I_B - \Delta i_b$ to $I_B + \Delta i_b$, so the operating point hops between higher and lower $I_B$ curves.

The constraint $V_{CE} = V_{CC} - I_C \cdot R_C$ still holds, so the operating point stays on the load line — it just slides up and down along it.

3.3 Output is inverted

When $I_C$ goes UP (because $v_{in}$ pushed $v_{be}$ UP), $V_{CE} = V_{CC} - I_C \cdot R_C$ goes DOWN. Hence the inverting nature of CE/CS.

The minus sign in the gain formula is the inversion:

3.4 Clipping — when you push too hard

If the input swing is large enough, the operating point hits a region boundary. At the top of the load line you crash into saturation ($V_{CE}$ collapses to ~0.2 V); at the bottom you fall into cut-off ($I_C \approx 0$).

The output flattens at those rails — that's clipping.

• Hit saturation (top of load line) — $V_{CE}$ clamped near 0.2 V. Output flat-tops at low $V_{out}$.
• Hit cut-off (bottom of load line) — $I_C \approx 0$, $V_{CE}$ pulled up to $V_{CC}$. Output flat-tops at high $V_{out}$.
• Stay in the active region — the only place the small-signal model holds. Outside the active region, $A_v$ formulas don't apply; the transistor behaves nonlinearly.

3.5 Why the Q-point at $V_{CC}/2$ maximises swing

Place the Q-point at $V_{CC}/2$ and the load-line distance to saturation equals the distance to cut-off. Equal headroom → maximum symmetric swing before clipping.

👉 Off-centre Q-point = lopsided swing room. Centred Q-point = full swing in both directions.

3.6 The same picture for FETs

The BJT construction above applies equally to a CS FET amplifier — just swap $i_B$ for $v_{GS}$ as the input variable and $V_{CE}$ for $V_{DS}$ at the output.

The key difference: the FET is a voltage-controlled device, so the input axis on the diagonal shows $v_{GS}(\omega t)$ — a voltage swing, not a current swing. No $V_{BE}$ drop to manage; the gate draws no DC current.

In the FET saturation region, $I_D \approx \frac{k}{2}(V_{GS}-V_{th})^2$— a square-law relationship. Small-signal gain is still $-g_m(R_D \| r_o)$, but $g_m = k(V_{GS}-V_{th})$ depends on the Q-point, whereas BJT $g_m = I_C/V_T$ scales purely with collector current.

👉 Both figures tell the same story: a small AC input tilts the operating point along a fixed load line, and the $V_{out}$ waveform on the bottom axis is always an inverted, amplified copy.

Simple analogy — a swing set with end stops

• The swing's resting position = the Q-point on the load line.
• The end stops = saturation (one side) and cut-off (the other).
• Pushing the swing too hard = the swing crashes into an end stop and stops moving smoothly — that's what clipping looks like at the output.
• Park the swing in the middle to use the full range without hitting either stop.

👉 Try it in the simulator — push the $V_{in}$ slider hard and watch the $V_{out}$ waveform clip when the swing exceeds the Q-point's headroom.

4. Input and output impedance

👉 Simple analogy — entrance and exit doors

• $R_{in}$ = how easy is it for the signal source to push current INTO the amp? Smaller $R_{in}$ = harder to drive.
• $R_{out}$ = how stiff is the output? Smaller $R_{out}$ = drives any load perfectly.
• An ideal voltage amp has infinite $R_{in}$ and zero $R_{out}$.

4.1 $R_{in}$ (BJT)

$R_{in} = R_1 \| R_2 \| r_{\pi}$. Typically a few kΩ — moderate but not huge.

4.2 $R_{in}$ (FET)

$R_{in} = R_{G1} \| R_{G2}$ (often hundreds of kΩ to MΩ). FETs are inherently high-impedance at the gate.

4.3 $R_{out}$ (both)

$R_{out} = R_C \| r_o$ (CE) or $R_D \| r_o$ (CS). Set mostly by $R_C$ / $R_D$ since $r_o$ is large.

Where:

• $r_{\pi} = \beta / g_m$ from Topic 1 — typically 1–5 kΩ at $I_C \approx 1\,\text{mA}$.
• $r_o = V_A / I_C$ from Topic 1 — typically 50–500 kΩ; usually larger than $R_C$ so it doesn't dominate.

5. The role of $R_E$ and $C_E$

Why $R_E$ exists (DC bias stability)

$R_E$ creates negative feedback at DC that prevents thermal runaway. If $I_C$ rises due to temperature, the voltage across $R_E$ increases, which reduces $V_{BE}$ — pulling the current back down. This self-correcting loop keeps the Q-point stable.

$R_E$ also improves linearity (less distortion) because the feedback linearises the exponential $I_C$–$V_{BE}$ relationship. The trade-off: it reduces AC gain unless bypassed.

Why $C_E$ exists (AC gain boost)

$C_E$ is connected in parallel with $R_E$. At signal frequencies it acts as a short circuit, effectively removing $R_E$ from the AC path. At DC the capacitor is open — $R_E$ still sets the bias.

• Without $C_E$ — emitter degeneration: lower gain, better stability and linearity.
• With $C_E$ — full $g_m R_C$ gain for AC, DC stability preserved via $R_E$.

The bypass capacitor in detail

👉 Simple analogy — a valve and a release pipe

• $R_E$ is a valve that fights signal swing (negative feedback).
• $C_E$ is a release pipe that bypasses the valve at signal frequencies.
• DC water still flows through the valve; AC water shortcuts around it.
• 👉 Bypass cap = full gain at signal frequencies; full bias stability at DC.

5.1 The problem

Without $C_E$, the emitter voltage moves with the signal, reducing the effective $v_{be}$ that drives the transistor. This negative feedback lowers gain.

5.2 The fix

Add $C_E$ in parallel with $R_E$. At signal frequencies $C_E$ acts as a short, holding the emitter at AC ground.

5.3 At DC, $C_E$ is open

DC bias is unaffected — the full $R_E$ sets the Q-point. This is the magic of “AC-only feedback bypass.”

6. A first taste of bandwidth — Miller effect

👉 Simple analogy — a pole vault landing pit that grows

• $C_{\mu}$ is a small landing pit at the input.
• High gain inflates the pit by $(1 + |A_v|)$ — the input now sees a huge soft landing zone.
• The bigger the pit, the longer it takes to land (lower bandwidth).
• 👉 The cascode (Topic 4) is the standard fix.

6.1 The catch

High gain has a price: the collector-base capacitance $C_{\mu}$ appears at the inputmultiplied by $(1 + |A_v|)$ — called the Miller effect.

6.2 Why

The output swings at $A_v$ times the input. The voltage across $C_{\mu}$ is therefore $(1 + |A_v|)$ times the input — drawing far more current at the input node.

6.3 Result

The CE / CS bandwidth rolls off at:

Where:

• $C_{\mu}$ — typically a few pF for a small-signal BJT.
• $R_S$ — the source resistance driving the amplifier.
• $|A_v|$ — the magnitude of the voltage gain.

Try it in the simulator

Open the Simulate tab to explore the CE & CS Amplifier interactively. Toggle the bypass capacitor to feel the difference between full gain and degenerated gain. Slide $R_L$ from high to low and watch the gain drop as the load draws more current. Increase $V_{in}$ until the $V_{out}$ waveform clips — that's the Q-point swing limit in action.