Transistor Small-Signal Models

1. The Q-point (your operating point)

The Q-point is the steady DC operating point — where the transistor sits when no signal is applied. Think of it as the transistor at rest.

2. The real behavior (curved)

A transistor does not behave in a straight line. The graph of $I_C$ vs $V_{BE}$ is curved (exponential), so small changes in voltage don't always give proportional changes in current.

That makes analysis difficult.

3. What happens when a small signal comes?

When you add a small AC signal, the transistor moves a tiny bit around the Q-point — not across the whole curve, just a small region.

4. The trick: tangent-line approximation

In that small region, the curve looks almost like a straight line. We replace the curved transistor with its tangent at Q.

The slope of that tangent is $g_m$ — the transconductance.

5. Why we do this

Straight lines are easy: Ohm's law, superposition, and every linear-circuit tool just works. Curves don't compose cleanly.

The price: this is only valid for small signals — push too hard and you wander off the tangent. That's clipping.

1. The input side (between Base and Emitter)

The resistor $r_{\pi}$ (r-pi) is like a small door between base (B) and emitter (E). When you apply a small voltage $v_{be}$, current flows through this door.

👉 Input voltage → small input current.

2. The amplifier action (the current source)

The circle labelled $g_m \cdot v_{be}$ is the main action. The transistor takes the small input voltage and creates a larger current at the output.

$g_m$ is just a number — bigger $g_m$, more output current per millivolt of input.

3. The output side (between Collector and Emitter)

In a BJT, ideally $I_C$ should stay constant no matter what $V_{CE}$ is.

But in reality, the Early effect kicks in. When $V_{CE}$ increases, the base region gets slightly thinner, so $I_C$ increases a little — even if $I_B$ is fixed.

👉 $r_o$ models this small dependence of $I_C$ on $V_{CE}$.

Putting it all together

• Input (B–E): small voltage enters
• Middle: transistor converts it into a larger current
• Output (C–E): current flows out, but not perfectly (because of $r_o$)

Simple analogy — water tap

• $r_{\pi}$ → small handle you turn (input control)
• $g_m \cdot v_{be}$ → mechanism that controls how much water flows
• $r_o$ → small leakage in the pipe

Where:

• $V_T$ is the thermal voltage — about 25 mV at room temperature. Every extra $V_T$ of $V_{BE}$ roughly triples $I_C$. For example, if $V_{BE}$ increases by 50 mV (2 × $V_T$), $I_C$ triples twice — about a 9× increase.
• $\beta$ (beta) is the current gain — typically 100 – 300, set by the device. It tells you how much collector current flows for a given base current.
• $V_A$ is the Early voltage (named after physicist James M. Early) — typically 50 – 150 V. A large $V_A$ means $r_o$ is large (close to the ideal current source).

Same idea, simpler picture — only two components.

1. The input side (Gate)

The FET gate is a sealed touch-pad — pressing it draws essentially no current.

👉 No $r_{\pi}$. The input side is just open.

This is the FET's superpower: extremely high input impedance.

2. The amplifier action (current source)

Same as the BJT: a current source $g_m \cdot v_{gs}$ at the output. Small voltage at the gate, larger current at the drain.

3. The output side

Same $r_o$ as the BJT — sits across the output, models the FET's version of the Early effect (called channel-length modulation).

Water-tap analogy, FET version

• No handle — replaced by a touchless capacitive sensor (no $r_{\pi}$)
• Same flow-control mechanism ($g_m \cdot v_{gs}$)
• Same small pipe leakage ($r_o$)

Where:

• $k_n$ is the transconductance parameter — typically a few mA/V², set by the device geometry and the process. Bigger $k_n$ = more “muscle”.
• $V_{OV} = V_{GS} - V_{th}$ is the overdrive voltage — how far the gate is pushed above the threshold. The bigger the overdrive, the harder the FET is on.
• $\lambda$ is the channel-length modulation factor — typically 0.01 – 0.05 V⁻¹. Small $\lambda$ means $r_o$ is large (close to ideal).

So far we know HOW to use the small-signal model. But where should you actually bias the transistor?

1. The problem — clipping at the rails

The output $V_{CE}$ can swing UP until it hits $V_{CC}$ (cutoff at the top) and DOWN until it hits about 0.2 V (saturation at the bottom). Bias too close to either rail and the signal clips.

2. The sweet spot — $V_{CE} \approx V_{CC}/2$

Park the Q-point at half-supply. The output now has equal headroom in both directions before clipping.

👉 Maximum symmetric output swing.

3. Simple analogy — the playground swing

Imagine you're parking a swing for a child:

• Park it pushed all the way forward → it can only swing backward (one-sided motion)
• Park it pushed all the way backward → it can only swing forward (one-sided motion)
• Park it in the middle → it can swing both ways equally

The Q-point is where you park the transistor's output before any signal arrives. $V_{CE} = V_{CC}/2$ is the middle of the swing.

4. Alternative — the rule of thirds

Some textbooks suggest a different bias split:

• $V_E \approx V_{CC}/3$ — gives stable bias against temperature drift
• $V_{R_C} \approx V_{CC}/3$ — voltage drop across $R_C$ sets the gain
• $V_{CE} \approx V_{CC}/3$ — leaves room for the output to swing

The two rules disagree on $V_{CE}$ ($V_{CC}/2$ vs $V_{CC}/3$). Pick based on goal:

• Maximise signal swing → use $V_{CC}/2$
• Minimise power dissipation ($P = V_{CE} \cdot I_C$) → bias $V_{CE}$ lower
• Balance both → rule of thirds

5. Keep $V_E \geq 1\,\text{V}$ for bias stability

A separate concern: the voltage across $R_E$ should be at least about 1 V. Why? $V_{BE}$ drifts ~2 mV per °C with temperature, so if $V_E$ is comparable to $V_{BE}$ (~0.7 V), small drifts shift $I_C$ noticeably.

With $V_E \geq 1\,\text{V}$, $R_E$ acts as negative feedback that absorbs $V_{BE}$ drift and keeps $I_C$ stable across temperature.

👉 Stable bias = predictable amplifier.

Try it in the simulator

Open the Simulate stage of this topic and watch the Q-point Guide panel — green when $V_{CE}$ lands near $V_{CC}/2$ (within ±20%), amber if off-target, red if saturated or cut off. Slide $R_C$, $R_E$, $R_1$, and $R_2$ — feel how the bias responds.

Up to here we've talked about the transfer curve ($I_C$ vs $V_{BE}$). The transistor also has an output curve — and that's where the load line lives.

1. The output characteristic — a family of curves

Each curve is the $I_C$ you'd get for one fixed $I_B$ as you sweep $V_{CE}$. Higher $I_B$ = higher curve.

Together they look like a stack of nearly-flat lines.

2. Three regions, three behaviours

• Saturation ($V_{CE} \lesssim 0.2\,\text{V}$) — $V_{CE}$ has collapsed. The transistor can't push more $I_C$; it's “stuck on”.
• Active ($V_{CE}$ between ≈ 0.2 V and $V_{CC}$) — the workhorse region. $I_C \approx \beta I_B$; the transistor amplifies cleanly.
• Cut-off ($I_B \approx 0$) — $I_C \approx 0$. Transistor is off.

3. The DC load line — what the circuit allows

The transistor doesn't choose its operating point alone — $V_{CC}$ and $R_C$ set a constraint: $V_{CE} = V_{CC} - I_C \cdot R_C$, a straight line on the $I_C$ / $V_{CE}$ plot.

The Q-point is where this load line crosses the chosen $I_B$ curve.

The load line runs between two end-points:

• When $I_C = 0$: $V_{CE} = V_{CC}$ → point B at ($V_{CC}$, 0)
• When $V_{CE} = 0$: $I_C = V_{CC}/R_C$ → point A at (0, $V_{CC}/R_C$)

4. Where the Q-point should sit

Pick $I_B$ (via the bias divider) so the Q-point lands at $V_{CE} \approx V_{CC}/2$ — middle of the load line. That gives equal swing room above and below for the AC signal.

👉 See the Picking the Q-point section above for the half-supply rule and the rule of thirds.

5. The FET version — same idea, different vocabulary

The FET has the same picture: a family of $I_D$ curves parametrised by $V_{GS}$, with a load line from $V_{DD}$ through $R_D$.

The only catch is the terminology.

• Triode region (FET) = roughly equivalent to BJT's saturation region — $V_{DS}$ too low, transistor compressed.
• Saturation region (FET) = roughly equivalent to BJT's active region — the good amplifier mode.

👉 FET “saturation” = good. BJT “saturation” = bad. Keep them straight.

Simple analogy — multi-lane highway with a speed-limit sign

• Each curve = one lane (one fixed control input — $I_B$ for BJT, $V_{GS}$ for FET).
• The load line = the speed limit forced by the engine and road conditions ($V_{CC}$, $R_C/R_D$).
• The Q-point = your steady cruising spot — pick the middle of your lane and in the middle of the speed range to leave room to accelerate up and coast down without crashing into the rail (saturation) or grinding to a halt (cut-off).

Open the simulator and watch the Q-point Guide — green when $V_{CE}$ lands near $V_{CC}/2$ (within ±20%) on the load line, amber if off-target, red if saturated or cut off.

1. Find the DC Q-point. Solve the bias network with large-signal equations to get $I_C$ (or $I_D$) and $V_{CE}$ (or $V_{DS}$).
2. Replace the transistor and short DC supplies. Substitute the hybrid-π (or FET) model for the transistor, replace every DC voltage source with a short circuit (AC ground), and replace DC current sources with opens.