Asynchronous Counters — worked examples

Digital Electronics · Asynchronous Counters · Example

Example 1: 3-bit ripple counter — full cycle

A 3-bit ripple counter starts at 000. Trace $Q_2 Q_1 Q_0$ for 8 clock edges (one full cycle).

Clock edge	Q2 Q1 Q0	Decimal
0 (start)	0 0 0	0
1	0 0 1	1
2	0 1 0	2
3	0 1 1	3
4	1 0 0	4
5	1 0 1	5
6	1 1 0	6
7	1 1 1	7
8	0 0 0	0

3 flip-flops produce

2^3 = 8

unique states (0 to 7). After the 8th clock edge the counter wraps back to 000.

Example 2: MOD-6 counter — what triggers reset?

You need a counter that cycles 0 through 5 and then wraps. Which count triggers the reset, and how many flip-flops do you need?

Step 1: MOD-6 means 6 states (0 to 5). You need at least $\lceil \log_2 6 \rceil = 3$ flip-flops.
Step 2: The counter should never display count 6. When it reaches 110 (six in binary), the reset gate fires immediately.
Step 3: Detect 110: connect $Q_2$ and $Q_1$ to a NAND gate. When both are high, assert async clear.

Clock	Q2 Q1 Q0	Decimal
0	0 0 0	0
1	0 0 1	1
2	0 1 0	2
3	0 1 1	3
4	1 0 0	4
5	1 0 1	5
6	0 0 0	0 (reset)

The counter briefly hits 110 (6) before the reset clears it. This happens so fast it is usually invisible, but it is a decode glitch.

Example 3: Maximum clock frequency

A 3-bit ripple counter uses flip-flops with $t_{pd} = 20\,\text{ns}$ each. What is the maximum clock frequency?

Step 1: Total ripple delay = $N \times t_{pd} = 3 \times 20\,\text{ns} = 60\,\text{ns}$ .
Step 2: The clock period must be longer than the total ripple delay, so $T_{\min} = 60\,\text{ns}$ .
Step 3: $f_{\max} = \frac{1}{T_{\min}} = \frac{1}{60 \times 10^{-9}} \approx 16.7\,\text{MHz}$ .

Each additional flip-flop in a ripple counter lowers the maximum operating frequency. For high-speed designs, synchronous counters avoid this bottleneck.