Asynchronous Counters

Digital Electronics · 12 min read

A counter is a register that increments (or decrements) its stored value on every clock edge. The simplest kind — the ripple counter — chains T flip-flops so each one toggles the next, like a row of falling dominoes. The toggle “ripples” through the chain, which is why these counters are called asynchronous: the flip-flops do not all change at the same time.

A T flip-flop with T = 1 is identical in behavior to a JK flip-flop with J and K both tied to logic 1 — both simply toggle on every active clock edge. Throughout this page we use T flip-flops because they make the counter operation most intuitive.

1. 2-Bit Ripple Counter

The external clock drives only FF0. The output of FF0 ( $Q_0$ ) drives the clock input of FF1. Each flip-flop has T = 1, so it toggles on every falling edge of its own clock.

Figure 1. 2-bit ripple counter: the system clock drives FF0, and Q0 drives the clock input of FF1. Each flip-flop toggles on its falling edge.

FF0 is clocked by the external clock. FF1 is clocked by $Q_0$ .
Each flip-flop has T = 1, so it toggles on every active clock edge.
Count sequence: 00 → 01 → 10 → 11 → 00 (wraps around).

Ripple Propagation Timing

This is the defining characteristic of asynchronous counters. Each $Q$ output changes slightly after its clock edge — not simultaneously. The small arrows below show the propagation delay ( $t_{pd}$ ) between each stage.

Figure 2. Timing waveform: CLK drives Q0, Q0 drives Q1. Notice Q0 changes one t_pd after the CLK edge, and Q1 changes one t_pd after Q0's edge. The ripple delay accumulates.

The ripple delay is what makes this counter asynchronous. Outputs do not all change at the same instant — each stage waits for the previous one to finish toggling.

Try It: Watch the Domino Effect

Click Clock and watch each flip-flop toggle in sequence — FF0 first, then FF1, then FF2 — like falling dominoes. The binary and decimal count update live.

3-bit ripple counter — domino effect

(decimal)

2. N-Bit Ripple Counter

Figure 3. Extending the chain: N T flip-flops create an N-bit ripple counter that counts from 0 to 2^N minus 1.

N flip-flops count from 0 to $2^N - 1$ , then wrap.
A 4-bit counter counts 0 to 15. An 8-bit counter counts 0 to 255.

Each Stage Divides the Frequency by 2

One of the most beautiful properties of a ripple counter: each flip-flop output toggles at exactly half the frequency of its input clock. This makes ripple counters natural frequency dividers.

Stage	Frequency	Division
CLK (input)	1 MHz	—
Q0 (FF0)	500 kHz	÷ 2
Q1 (FF1)	250 kHz	÷ 4
Q2 (FF2)	125 kHz	÷ 8
Q3 (FF3)	62.5 kHz	÷ 16

Figure 4. Frequency division in a 4-stage ripple counter (1 MHz input clock example).

A ripple counter is both a binary counter and a frequency divider. Stage N divides the input clock by

2^{N+1}

3. MOD-N Counters

What if you need to count 0–9 instead of 0–15? You detect a chosen count and force the counter back to zero before it reaches its natural maximum. This truncation gives a “MOD-N” counter — one that cycles through exactly N states.

Figure 5. MOD-10 decade counter: a NAND gate detects count 1010 (ten) and asynchronously resets all flip-flops to 0000.

The NAND gate watches $Q_3$ and $Q_1$ . When both go high the count has reached 1010 (ten in binary).
The NAND output goes low, asserting the active-low $\overline{\text{CLR}}$ on every flip-flop, resetting the count to 0000.
If the flip-flops use an active-high reset instead, replace the NAND gate with an AND gate — the AND output goes high when the target count is reached, driving CLR directly.
The counter cycles: 0000 → 0001 → … → 1001 → (briefly 1010) → 0000.

The target state (1010) appears briefly before the reset propagates. This transient “glitch” is unavoidable in ripple counters because the reset itself takes time to propagate.

MOD-10 Reset Timing

Here is what actually happens during the reset transition. The count reaches 1001 (nine). On the next clock edge:

Figure 6. MOD-10 reset glitch: the counter briefly shows 1010 before the NAND gate propagates the reset.

FF0 toggles: 1001 → 1010. This is the target count — NAND detects it.
After a short gate delay, NAND asserts RESET.
After another propagation delay, all FFs clear to 0000.
Total glitch width ≈ NAND delay + FF clear delay (typically 10–30 ns).

4. The Ripple Delay Problem

Figure 7. Propagation delay accumulates: each flip-flop adds its own t_pd before the next stage sees the edge.

Each flip-flop adds its own $t_{pd}$ before the next one sees the clock edge.
Total delay for an N-bit counter: $t_{\text{total}} = N \times t_{pd}$ .

Maximum Clock Frequency

The clock must be slow enough for the ripple to settle before the next edge arrives:

f_{\max} = \frac{1}{N \times t_{pd}}

Worked example: 4-bit counter,

t_{pd} = 15\,\text{ns}

per FF → total ripple delay = 60 ns → max clock =

\frac{1}{60\,\text{ns}} \approx 16.7\,\text{MHz}

This speed limit is the main drawback of ripple counters. As N grows, the maximum frequency drops — making large ripple counters impractical for high-speed designs.

5. Decode Glitches

Figure 8. During the ripple from 0111 to 1000, intermediate states briefly appear — any combinational decode logic may produce false outputs.

When counting from 0111 to 1000, the bits don’t all change at once. You might briefly see 0110, 0100, 0000 before reaching 1000.
Any combinational decode logic connected to the outputs can trigger falsely during these transient states.

6. Up vs Down Counting

Figure 9. Up counter: Q drives the next clock. Down counter: the complement output Q-bar drives the next clock.

Up counter: use Q to clock the next flip-flop. Count increments.
Down counter: use $\overline{Q}$ to clock the next flip-flop. Count decrements.

7. The T Flip-Flop — The Natural Counter FF

For counters, the T (toggle) flip-flop is the simplest and most intuitive choice. With T = 1, it simply toggles on every clock edge:

Q_{\text{next}} = T \oplus Q

T flip-flop (T = 1): Conceptually simplest for teaching. Just toggles.
JK flip-flop (J = K = 1): Same toggle behavior. Historically the most common counter FF in discrete logic.
D flip-flop: Dominant in modern FPGA/ASIC designs. Counter logic uses combinational next-state equations:

D_0 = \overline{Q_0}, \quad D_1 = Q_1 \oplus Q_0

For learning, T flip-flops are the clearest way to understand counters. Real digital systems usually implement counters with D flip-flops and combinational next-state logic.

8. Synchronous vs Asynchronous

Why do synchronous counters exist if ripple counters are simpler? The table below explains the trade-off:

Property	Asynchronous	Synchronous
Clocking	Each FF clocked by previous Q	All FFs share one clock
Speed	Limited by N × t_pd	Limited by single t_pd
Glitches	Transient invalid states	Clean transitions
Complexity	Simpler wiring	Needs carry logic
Max frequency	Low (decreases with N)	High (constant)
Best for	Low-speed, frequency division	High-speed, glitch-free

Figure 10. Asynchronous vs synchronous counter comparison.

9. Counter Applications

Counter type	Real-world uses
Ripple counter	Frequency dividers, low-speed event counting
MOD-10 (decade)	Digital clocks, BCD displays, odometers
MOD-N (arbitrary)	Baud rate generators, prescalers, timers
Up/down counter	Position encoders, bidirectional tracking
Frequency divider	Clock distribution, PLL reference division

Figure 11. Common counter types and where they are used in real systems.