Latches & Flip-Flops — worked examples

Digital Electronics · Latches & Flip-Flops · Example

Example 1: SR latch — trace Q through a sequence

An SR latch starts with Q = 0. Apply the following input sequence and determine Q after each step.

Step	S	R	Q	Reason
Initial	—	—	0	Given
1	1	0	1	Set
2	0	0	1	Hold
3	0	1	0	Reset
4	0	0	0	Hold

Figure 1. SR latch input sequence and resulting Q values.

Step 1: S = 1, R = 0 — the Set input is active, so Q goes to 1.
Step 2: S = 0, R = 0 — both inputs inactive, latch holds. Q stays at 1.
Step 3: S = 0, R = 1 — the Reset input is active, so Q goes to 0.
Step 4: S = 0, R = 0 — both inputs inactive again. Q holds at 0.

Example 2: D flip-flop — Q at each rising edge

A positive-edge-triggered D flip-flop starts with Q = 0. Given the CLK and D waveforms below, determine Q after each rising edge.

Figure 2. CLK and D waveforms with Q captured at each rising edge. Rising edges occur at time slots 1, 3, 5, and 7.

Edge 1 (slot 1): D = 1 at the rising edge. $Q \leftarrow 1$ .
Edge 2 (slot 3): D = 1 at the rising edge. $Q \leftarrow 1$ (no change).
Edge 3 (slot 5): D = 0 at the rising edge. $Q \leftarrow 0$ .
Edge 4 (slot 7): D = 1 at the rising edge. $Q \leftarrow 1$ .

Only the value of D at the rising edge matters. D can change freely between edges without affecting Q.

Example 3: JK flip-flop — toggle behaviour

A JK flip-flop starts with Q = 0 and has J = 1, K = 1 held constant. What happens over 4 consecutive rising clock edges?

Figure 3. With J = K = 1, the JK flip-flop toggles on every rising edge: 0 → 1 → 0 → 1 → 0.

Edge 1: J = 1, K = 1, Q = 0 — toggle. $Q \leftarrow 1$ .
Edge 2: J = 1, K = 1, Q = 1 — toggle. $Q \leftarrow 0$ .
Edge 3: J = 1, K = 1, Q = 0 — toggle. $Q \leftarrow 1$ .
Edge 4: J = 1, K = 1, Q = 1 — toggle. $Q \leftarrow 0$ .

This toggle behaviour is exactly what counters need — a JK flip-flop with J = K = 1 divides the clock frequency by 2. Chain four of them and you get a 4-bit ripple counter.