Latches & Flip-Flops

Digital Electronics · 12 min read

Digital Logic 101 covered combinational circuits — their output depends only on the current inputs. But what if a circuit needs to remember?

A traffic-light controller must know which light is currently on. A counter must know its current count. Sequential circuits add memory, and the fundamental memory element is the latch.

1. SR Latch

The SR (Set-Reset) latch is the simplest memory element. It stores one bit and offers two controls: S to set the output to 1, and R to reset it to 0.

Figure 1. Gate-level SR latch: two cross-coupled NOR gates. Top gate output is Q̅, bottom gate output is Q. Setting S = 1 forces Q̅ = 0, which drives Q = 1 (set). Setting R = 1 forces Q = 0 (reset).

S	R	Q	Action
0	0	Q (hold)	No change
1	0	1	Set
0	1	0	Reset
1	1	??	Forbidden

Figure 2. SR latch truth table.

The forbidden state occurs when S = 1, R = 1. Both NOR gate outputs go low, so Q and

\overline{Q}

are both 0 — contradicting the rule that they must be complements.

Worked trace: start with Q = 0. Apply [S=1, R=0] — Q becomes 1. Then [S=0, R=0] — Q holds at 1. Then [S=0, R=1] — Q resets to 0. Finally [S=0, R=0] — Q holds at 0.

NAND-Gate Implementation — Active-Low Inputs

The same feedback topology works with NAND gates, but the logic is inverted: the inputs become active-low. Pulling S LOW sets Q, and pulling R LOW resets Q. When both inputs sit HIGH the latch holds its state — the normal idle condition.

Figure 3. NAND-gate SR latch. Inputs S and R are active-low. The output bubble on each NAND gate inverts the signal, so a LOW on S forces Q̄ HIGH, which drives Q LOW through the bottom gate — effectively setting Q = 1.

S	R	Q	Action
1	1	Q (hold)	No change (idle)
0	1	1	Set
1	0	0	Reset
0	0	??	Forbidden

Figure 4. NAND SR latch truth table. Active-low: a logic 0 on S or R activates Set or Reset.

The NAND latch's forbidden state is

\overline{S} = \overline{R} = 0

— both inputs LOW simultaneously. Both NAND outputs go HIGH, so Q and

\overline{Q}

are both 1. This is widely used in switch-debounce circuits because push-buttons naturally produce a LOW signal when pressed.

Worked trace (active-low): start with Q = 0. Apply [S=0, R=1] — Q becomes 1 (set). Then [S=1, R=1] — Q holds at 1. Then [S=1, R=0] — Q resets to 0. Finally [S=1, R=1] — Q holds at 0.

2. D Latch

The SR latch has a forbidden state. The D latch fixes this by providing a single data input D and an Enable (EN) control.

Figure 5. D latch block symbol. When EN is high, Q follows D (transparent). When EN goes low, Q freezes at whatever D was.

EN	D	Q
0	X	Q (hold)
1	0	0
1	1	1

Figure 6. D latch truth table.

“Transparent when enable is high” means data passes straight through. This is useful, but it creates a problem when multiple latches share a clock.

3. Edge Triggering — Why Latches Aren't Enough

The transparent latch problem

A latch is level-sensitive. When CLK (or EN) is HIGH, the latch is “open” — output Q follows input D continuously. Any change on D immediately appears at Q.

When CLK goes LOW, the latch “closes” — Q freezes at whatever value D had just before CLK fell.

Why is this a problem?

If two latches share the same clock and the output of Latch A feeds the input of Latch B, a signal can pass through both latches during one clock HIGH period. This is called a race-through or race condition — data moves farther than intended in one cycle.

The flip-flop solution

A flip-flop is edge-triggered. It samples the input only at the clock edge (usually the rising edge ↑). After that instant, the output stays fixed — even if D keeps changing. This prevents race-through completely.

See the difference — latch vs flip-flop

Watch what happens when D changes multiple times while CLK is HIGH:

Figure 7. Latch vs flip-flop. Green shading = CLK HIGH (latch transparent). The latch follows every D change during HIGH (amber). The flip-flop samples D only at the rising edge (green arrows) and ignores all other changes.

Latch (amber): Q follows D continuously while CLK is HIGH — every glitch on D passes through
Flip-flop (green): Q changes only at the rising edge ↑ — all other D changes are ignored

How a flip-flop is built — the master-slave concept

A flip-flop is typically built from two latches in series: the “master” latch is transparent when CLK is HIGH, and the “slave” latch is transparent when CLK is LOW.

Figure 8. Master-slave D flip-flop. The master latch captures D while CLK is HIGH. When CLK falls, the master closes and the slave opens, passing the captured value to Q. The two latches are never open simultaneously.

CLK HIGH: Master is transparent (D passes to X), slave is closed (Q holds)
CLK LOW: Master closes (X holds), slave opens (X passes to Q)
Result: Q updates once per cycle, at the falling edge of CLK (from master's perspective) — which is the effective rising-edge trigger of the overall flip-flop

Key takeaway

Latches can allow uncontrolled propagation during an entire clock level. Flip-flops stop propagation except at discrete clock edges — that is why every synchronous digital system uses flip-flops, not latches, as its core storage elements.

4. D Flip-Flop

Figure 9. IEEE Std 91 D flip-flop symbol. The triangle at the clock input indicates positive-edge triggering.

CLK	D	Q (next)
No edge	X	Q (hold)
Rising	0	0
Rising	1	1

Figure 10. D flip-flop truth table (positive-edge triggered).

Figure 11. Timing diagram: Q captures D at each rising clock edge and holds until the next edge.

On the rising edge, Q takes the value of D and holds it. Changes to D between edges are ignored — this is what makes flip-flops safe for synchronous design.

5. JK Flip-Flop

Figure 12. IEEE Std 91 JK flip-flop symbol. J and K inputs replace S and R.

J	K	Q (next)	Action
0	0	Q	Hold
1	0	1	Set
0	1	0	Reset
1	1	Q	Toggle

Figure 13. JK flip-flop truth table.

The JK flip-flop solves the forbidden state problem. When J = K = 1, the output toggles instead of entering an invalid state.

J = 0, K = 0 — hold (no change)
J = 1, K = 0 — set (Q = 1)
J = 0, K = 1 — reset (Q = 0)
J = 1, K = 1 — toggle (Q flips)

6. T Flip-Flop

Figure 14. IEEE Std 91 T flip-flop symbol. A single toggle input T.

T	Q (next)	Action
0	Q	Hold
1	Q	Toggle

Figure 15. T flip-flop truth table.

The T flip-flop is a special case of the JK flip-flop with J = K = T. When T = 0, Q holds; when T = 1, Q toggles. This makes it ideal for building counters.

7. Excitation Tables

A truth table answers “given these inputs, what is the next state?” An excitation table works backwards: “to get a desired state transition, what inputs do I need?”

Excitation tables are essential for designing sequential circuits. When you know the desired state transitions, the excitation table tells you what to connect to each flip-flop's inputs.

D Flip-Flop

Q	Q(next)	D
0	0	0
0	1	1
1	0	0
1	1	1

JK Flip-Flop

Q	Q(next)	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

T Flip-Flop

Q	Q(next)	T
0	0	0
0	1	1
1	0	1
1	1	0

Figure 16. Excitation tables for D, JK, and T flip-flops. Each row shows a desired transition and the required input(s).

D: Always set D equal to the desired next state — $D = Q_{\text{next}}$ .
JK: Multiple input combinations can produce the same transition, giving design flexibility.
T: T = 0 when you want to hold, T = 1 when you want to toggle.