Adders & Subtractors — worked example
Digital Logic 101 · Adders & Subtractors · Example
Example 1: (+5) + (−3) in 4-bit two's complement
- Encode the operands. Positive values are their plain binary patterns; negate by inverting and adding 1.
- Column-add LSB to MSB. Treat the bits as unsigned for the add; the two's-complement interpretation comes back at the end.The bit that falls off the MSB is the carry-out.
- Read the flags. The 4-bit result is . Carry-out = (a bit fell off the top).
- Overflow check. Operand signs are — they disagree, so overflow is impossible. Equivalently, the carry into the MSB column is and the carry out is ; .
Example 2: (+7) + (+1) in 4-bit two's complement
- Encode the operands. Both positive, both already in binary.
- Column-add.
- Read the flags. 4-bit result is . As an unsigned value that's , but as 4-bit signed it's . Carry-out = .
- Overflow check. Operand signs are but the result sign is . Signed overflow. Carry into MSB = ; carry out of MSB = ; .
In 4-bit signed arithmetic, the legal result range is ... The true sum doesn't fit, so the bits land at — wrapping past the top of the positive range and into the negative range. That's exactly what the overflow flag is reporting.
Try other operands in the Simulate stage — toggle the bits, flip the subtract switch, and watch the flags update live.