Adder & Subtractor

Step from a single-bit half/full adder up to a 4-bit two's-complement add/subtract datapath. Toggle inputs, watch the carry chain ripple, and see the overflow flag flip when the signed result outgrows the word.

Outputs:Sum = 0C_out = 0

0 + 0 = 0 (binary 00)

Binary adders

Binary addition follows the same column-by-column rule as decimal addition, but with only two digits: 0+0=0, 0+1=1, 1+1=10 (sum 0 carry 1), 1+1+1=11 (sum 1 carry 1). The carry propagates to the next more-significant bit.

Half adder vs full adder

Half adder: two inputs (A, B), two outputs. Sum = A ⊕ B, Carry = A · B. Cannot accept a carry-in — only usable for the LSB.
Full adder: three inputs (A, B, C_in), two outputs. Built from two half adders + an OR gate for carry-out. Required for all higher bit positions.

Ripple-carry vs carry-lookahead

A ripple-carry adder chains n full adders; the carry must propagate through every stage before the result is valid — delay grows linearly with bit width. Carry-lookahead adders compute carry signals in parallel using generate (G = A · B) and propagate (P = A ⊕ B) terms, reducing delay to O(log n).

Worked example — 4-bit addition

Add 0110 (6) + 0101 (5). Working right-to-left, a chain of full adders carries between columns: bit 0 → 0+1=1 (carry 0); bit 1 → 1+0=1 (carry 0); bit 2 → 1+1=0 carry 1; bit 3 → 0+0+1(carry)=1. Result 1011 = 11. Notice the carry rippling out of bit 2 into bit 3 — that dependency is exactly why a ripple-carry adder's worst-case delay scales with bit width.

Common questions

How does the same circuit subtract?: In two's-complement, A − B = A + (~B) + 1. Invert every bit of B and force the LSB carry-in to 1; the adder then produces the difference. A single XOR per bit, controlled by an "add/subtract" line, flips B on demand.
What is overflow, and how is it detected?: Signed overflow happens when the result exceeds the range the bit width can represent. It is flagged when the carry into the sign bit differs from the carry out of it (V = C_in ⊕ C_out of the MSB).

Learn more → Logic Gates — Learn

Quick experiments

Find the half adder's blind spot. Add 1 + 1 on a half adder: sum 0, carry 1. Correct on its own, but there is no carry-in, so it cannot be chained. That single missing input is what a full adder supplies.
Watch the carry ripple. Add 0111 + 0001 on a 4-bit ripple adder. The carry has to travel through every stage before the top bit settles — the worst case, and the reason wide adders use carry-lookahead.
Subtract with the same hardware. Invert the second operand and set carry-in to 1. Try 5 − 3: A = 0101, NOT B = 1100, carry-in 1 gives 0010 = 2. One circuit, both operations.
Trigger a signed overflow. Add 0111 + 0001 in 4-bit signed. The result 1000 reads as −8, not +8. The carry into the MSB differs from the carry out, which is exactly what the overflow flag detects.
See carry-out and overflow disagree. Add 1111 + 0001 signed: that is −1 + 1 = 0, correct, yet carry-out is 1. Carry-out flags unsigned overflow only — the two flags answer different questions.

Formula reference

Half adder: $S = A \oplus B \qquad C_{out} = A \cdot B$
Two bits in, sum and carry out. No carry-in.
Full adder: $S = A \oplus B \oplus C_{in}$
Three inputs, so full adders can be chained.
Full adder carry: $C_{out} = A B + C_{in}(A \oplus B)$
Carry out when both bits are 1, or when one is and a carry came in.
Signed overflow: $V = C_{n} \oplus C_{n-1}$
Carry into the sign bit differs from the carry out of it.

Symbol	Meaning	Unit
$S$	Sum bit	—
$C_{in}$	Carry into the stage	—
$C_{out}$	Carry out of the stage	—
$V$	Signed overflow flag	—

Common mistakes

Chaining half adders to build a multi-bit adder.
A half adder has no carry-in, so from the second stage onward it cannot accept the previous carry. Only the least significant bit may use a half adder; every other stage needs a full adder.
Treating carry-out as the overflow flag.
Carry-out indicates unsigned overflow; V indicates signed overflow. Adding −1 and 1 sets carry-out with a perfectly correct result, so using it as an error flag produces false alarms.
Subtracting without setting carry-in to 1.
Two's complement is invert plus one. Inverting B but leaving carry-in at 0 computes A − B − 1, an answer that is off by exactly one and easy to miss.
Using OR instead of XOR for the sum.
The sum bit must be 0 when both inputs are 1, because that case carries. OR gives 1 there, so 1 + 1 comes out as 3 rather than 2.
Assuming a wider ripple-carry adder is just as fast.
Ripple-carry delay grows with word width, since the top bit cannot settle until the carry has passed through every stage. Wide, fast adders need carry-lookahead or a carry-select structure.

Frequently asked questions

What is the difference between a half adder and a full adder?

A half adder adds two bits and produces a sum and a carry, but has nowhere to accept a carry coming in. A full adder takes three inputs — two bits plus a carry-in — so it can be chained to add multi-bit numbers.

How does a ripple-carry adder work?

Full adders are chained so each stage's carry-out feeds the next stage's carry-in. It is simple and compact, but the carry has to propagate through every stage, so the worst-case delay grows in proportion to the word width.

How do I subtract using an adder?

Invert every bit of the second operand and set the carry-in to 1. That forms the two's complement, so A plus NOT B plus 1 equals A minus B, and one circuit handles both operations.

How do I detect signed overflow?

Overflow occurred if the carry into the most significant bit differs from the carry out of it, which is an XOR of those two carries. Equivalently, adding two positives gave a negative, or adding two negatives gave a positive.

Why is carry-out not the same as overflow?

Carry-out signals unsigned overflow, meaning the result exceeded the unsigned range. Overflow signals signed overflow, meaning the result left the two's complement range. Either can occur without the other.