Flip-Flop Simulator

D, JK, T, SR and active-low SR — toggle the inputs, clock the device, and watch the waveform build up underneath. Each type shows its own next-state equation, characteristic table and excitation table, so you can read the behaviour both ways round.

Inputs

Auto-clock

Outputs

Next-state equation:

Q_{next} = D

Timing Waveform

Press Clock or enable Auto-clock to start recording

One bit of memory, five ways to control it

A flip-flop stores exactly one bit. What separates the types is not what they remember but how you tell them what to remember. A D type takes the value directly, so Q_next = D and there is nothing to think about. A T type toggles when told to, which makes it a natural counter stage. A JK type can set, reset, hold or toggle, so it does everything — at the cost of two inputs to plan. SR is the primitive underneath them all, and the one with a forbidden state.

Latches are level-triggered; flip-flops are edge-triggered

A latch is transparent for as long as its enable is active — the output follows the input the whole time. A flip-flop samples only at a clock edge and then ignores its input until the next one. That distinction is what makes synchronous design work: every device in the system changes at the same instant, so the logic between them has a whole clock period to settle.

Characteristic and excitation tables read in opposite directions

The characteristic table answers “given these inputs, what does Q become?” — it is for analysis. The excitation table answers “I want Q to go from 0 to 1, what must I drive?” — it is for design, and it is the table you actually use when building a counter or a state machine. The excitation table is where JK earns its keep: its don’t-care entries mean fewer gates in the logic that feeds it.

Learn more → Latches & Flip-Flops — Learn

Quick experiments

Watch a D type ignore its input between edges. Pick D, set D = 1 and clock once — Q goes high. Now flip D back and forth without clocking. Q does not move. That indifference between edges is the whole point of edge triggering.
Turn a JK into a T type. Select JK and set both J and K to 1. Every clock now flips Q. Tie J and K together and you have literally built a T flip-flop — which is why JK is called the universal type.
Make a JK hold. Set J = 0 and K = 0, then clock repeatedly. Q never changes. The four JK input combinations map exactly onto the four things a bit can do: hold, reset, set and toggle.
Find the SR forbidden state. Choose SR and set S = 1 and R = 1. The widget flags it, because you are asking the device to be set and reset at once — Q and Q̄ stop being complements and the next state depends on which input releases first. JK exists to make this case toggle instead.
See why active-low SR looks inverted. Switch to SR active-low. The inputs rest at 1 and you assert by pulling one to 0. It is the same latch built from NAND gates instead of NOR, which is why the polarity flips — and why datasheets bar the pin names.

Formula reference

D flip-flop: $Q_{next} = D$
The input, one edge later. No decoding needed.
T flip-flop: $Q_{next} = T \oplus Q$
Toggles when T = 1, holds when T = 0.
JK flip-flop: $Q_{next} = J\overline{Q} + \overline{K}Q$
Hold, reset, set and toggle across the four input codes.
SR flip-flop: $Q_{next} = S + \overline{R}\,Q \quad (S \cdot R = 0)$
The constraint is part of the definition, not a footnote.
Maximum clock frequency: $f_{max} = \frac{1}{t_{pd} + t_{su}}$
Propagation out of one stage plus setup into the next.

Symbol	Meaning	Unit
$Q$	Current stored bit	—
$Q_{next}$	Bit after the next clock edge	—
$t_{su}$	Setup time before the edge	ns
$t_{pd}$	Clock-to-output propagation delay	ns

Common mistakes

Treating a latch and a flip-flop as the same component.
A latch is transparent while enabled, so its output follows the input continuously. A flip-flop samples only on an edge. Substituting one for the other produces a circuit that works in simulation and races unpredictably in hardware.
Driving S = 1 and R = 1 on an SR flip-flop.
That state is forbidden, not merely discouraged. Q and Q̄ both go to the same level, and which state it lands in when you release depends on gate delays — genuinely unpredictable. Use JK if you need that input combination to mean something.
Reading the excitation table as if it were the characteristic table.
They run in opposite directions. Characteristic goes inputs to next state, for analysis. Excitation goes desired transition to required inputs, for design. Using the wrong one gives logic that is exactly inverted.
Assuming the output changes the instant the clock edge arrives.
There is a propagation delay after the edge, and the input must have been stable for the setup time before it. Those two numbers set the maximum clock frequency; ignoring them is the usual cause of a design that fails only at speed.
Forgetting that asynchronous preset and clear ignore the clock entirely.
They act the moment they are asserted, edge or no edge. That is useful for power-on reset and dangerous everywhere else — an async clear released near a clock edge can violate recovery time and put the device in a metastable state.

Frequently asked questions

What is the difference between a latch and a flip-flop?

A latch is level-triggered: while its enable is active the output follows the input continuously. A flip-flop is edge-triggered: it samples only at a clock edge and then ignores its input until the next one. That is what lets every device in a synchronous system change at the same instant.

Why is the JK flip-flop called universal?

Its four input combinations cover everything a stored bit can do: hold, reset, set and toggle. Tying J and K together gives you a T flip-flop, and driving K with the inverse of J gives you a D flip-flop, so JK can be wired to behave as either.

What is the forbidden state of an SR flip-flop?

Setting S and R both to 1 asks the device to set and reset at the same time. Q and its complement both go to the same level, and when you release the inputs the final state depends on which one changes first, which is a gate-delay race. JK was designed so that this combination toggles instead.

What is the difference between a characteristic table and an excitation table?

They read in opposite directions. A characteristic table answers what Q becomes given the inputs, which is analysis. An excitation table answers what inputs are needed to produce a wanted transition, which is design, and it is the one you use when building counters and state machines.

What limits how fast a flip-flop can be clocked?

The clock-to-output propagation delay plus the setup time of whatever it feeds, plus any logic in between. Those add to give the minimum clock period, so a device with 10 nanoseconds of propagation and 5 of setup tops out near 66.7 megahertz.