Static Hazard Analyzer
Watch a static-1 glitch appear on F = A·B + A'·C when A toggles with B = C = 1. Adjust per-gate delays, then add the B·C consensus term and see the hazard disappear.
Static hazards in combinational logic
A static hazard is a brief unwanted glitch — the output momentarily takes the wrong value during a transition between two input states that should both produce the same output. Even though the final value is correct, the glitch can clock downstream flip-flops.
Static-1 vs static-0 hazard
- Static-1 hazard: output should stay at 1 during the transition but briefly goes to 0.
- Static-0 hazard: output should stay at 0 but briefly spikes to 1.
How to eliminate static-1 hazards
On a K-map, a static-1 hazard occurs whenever two adjacent 1-groups are not covered by a single spanning group. Add a hazard-cover group that bridges the two existing groups — this adds a redundant product term to the SOP expression but eliminates the glitch. The cover group changes the circuit logic but not its steady-state truth table.
Learn more → Karnaugh Maps — Learn
Quick experiments
- Make the glitch appear. Hold B = C = 1 and toggle A. Algebraically the output should stay at 1 the whole time, but the waveform dips — for one propagation delay, neither product term is asserting.
- Find who is late. Increase the delay on the inverter feeding A'. The glitch widens, because the gap is exactly the window where A has already fallen but A' has not yet risen.
- Fix it with a redundant term. Add the consensus term B·C. It is logically redundant — it changes nothing in the truth table — but it holds the output high across the switch, and the glitch disappears.
- Confirm it is not a timing coincidence. With the consensus term in place, vary the gate delays again. The output stays clean regardless, which is the whole point: the fix is structural, not a delay you tuned.
Static hazards — reference
A hazard is a momentary wrong output produced by a circuit that is logically correct. It happens because signals arrive at different times: a single input change reaches one gate through an inverter and another gate directly, and for a few nanoseconds the two paths disagree.
The three kinds
A static-1 hazard is a brief dip to 0 when the output should stay at 1 — the case this tool demonstrates. A static-0 hazard is the mirror image, a brief spike to 1 when the output should stay at 0; it appears in product-of-sums circuits. A dynamic hazard is an output that changes more than once when it should change exactly once, and it needs three or more differing path delays to occur.
Why the K-map predicts it
On a Karnaugh map, a static-1 hazard lives wherever two adjacent 1-cells are covered by different prime implicants with no single group spanning both. Moving between those cells means handing the output from one product term to another, and if the hand-off is not overlapping, the output drops in between. Circling a redundant group that covers both cells is exactly the consensus term.
When it actually matters
In fully synchronous logic, usually not: a glitch that settles before the next clock edge is invisible to a flip-flop sampling on that edge. It matters when combinational output drives something edge-sensitive or level-sensitive — a clock, an asynchronous reset or preset, a latch enable, a counter's count input, or an output pin driving external hardware. A glitch on an asynchronous reset will reset the circuit, and no amount of reasoning about the truth table will explain it.
The cost of the fix
Consensus terms add gates that a minimiser would delete, so hazard-free logic is deliberately non-minimal. Synthesis tools optimise for area and will happily remove them unless told otherwise — which is why hazard-sensitive paths are usually handled by registering the signal instead, and glitch-free combinational design is reserved for cases where you cannot.
Common mistakes
Assuming a minimal expression is hazard-free.
Minimisation removes exactly the redundant terms that suppress hazards. The hazard-free form is often deliberately larger than the minimal one.
Treating hazards as a simulation artefact.
Glitches are real analogue pulses caused by unequal path delays. A functional simulator with zero delay will not show them; the hardware still produces them.
Adding redundant terms at random.
The extra term must cover the specific K-map transition between two adjacent groups. A term that covers nothing on the boundary adds gates and fixes nothing.
Worrying about hazards on ordinary synchronous data paths.
A clocked flip-flop samples after the logic settles, so glitches between edges are harmless. Reserve the effort for asynchronous logic, clocks, resets and enables.
Feeding combinational logic straight into a clock input.
A glitch on a clock line is counted as an edge. Clock signals must come from a clock tree or a registered output, never from raw combinational logic.
Frequently asked questions
What is a static hazard in digital logic?
A static hazard is a brief unwanted pulse on an output that should have stayed constant. It happens when one input change reaches parts of the circuit by paths of different delay, so the gates momentarily disagree.
What is the difference between a static-1 and a static-0 hazard?
A static-1 hazard is a momentary dip to 0 on an output that should have remained 1. A static-0 hazard is a brief spike to 1 on an output that should have remained 0. Sum-of-products circuits tend to produce static-1 hazards.
How do I eliminate a static hazard?
Add a redundant product term that covers the transition between two adjacent K-map groups. The term is logically unnecessary but it holds the output steady while the other paths settle.
Do hazards matter in synchronous designs?
Usually not, because a clocked flip-flop only samples after the logic has settled. Hazards do matter for asynchronous logic, clock and reset lines, and any signal that drives an edge-triggered input directly.
What is a dynamic hazard?
A dynamic hazard is an output that changes more than once during a single intended transition, for example 0 to 1 to 0 to 1. It arises from three or more paths of differing delay and generally signals a poorly structured multi-level circuit.
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