Registers & Shift Registers — worked examples
Digital Electronics · Registers & Shift Registers · Example
Example 1: SISO — shifting in 1, 0, 1, 1
A 4-bit SISO shift register starts at 0000. We shift in the bits 1, 0, 1, 1 (MSB first). Show the register state after each clock edge.
- Clock 1: Shift in 1. Register:
1 0 0 0. Serial out: 0. - Clock 2: Shift in 0. Register:
0 1 0 0. Serial out: 0. - Clock 3: Shift in 1. Register:
1 0 1 0. Serial out: 0. - Clock 4: Shift in 1. Register:
1 1 0 1. Serial out: 0.
After 4 clock cycles the register holds
1 1 0 1. The original MSB (1) has reached the serial output position and will appear on the next clock edge.Example 2: 4-bit ring counter states
A 4-bit ring counter is preset to 1 0 0 0. List every state in the cycle.
| Clock | Q3 Q2 Q1 Q0 |
|---|---|
| 0 (preset) | 1 0 0 0 |
| 1 | 0 1 0 0 |
| 2 | 0 0 1 0 |
| 3 | 0 0 0 1 |
| 4 | 1 0 0 0 |
4 flip-flops = 4 unique states. The single 1 circulates endlessly, returning to the starting position after N clocks.
Example 3: 3-bit Johnson counter states
A 3-bit Johnson counter starts at 0 0 0. The complement of Q2 feeds back to the D input of FF0. List all states.
| Clock | Q2 Q1 Q0 |
|---|---|
| 0 (initial) | 0 0 0 |
| 1 | 1 0 0 |
| 2 | 1 1 0 |
| 3 | 1 1 1 |
| 4 | 0 1 1 |
| 5 | 0 0 1 |
| 6 | 0 0 0 |
3 flip-flops produce 2 x 3 = 6 unique states. The sequence fills with 1s from the left, then empties back to 0s — only one bit changes per clock, so outputs are glitch-free.