Timing Analysis — worked examples

Digital Electronics · Timing Analysis · Example

Example 1: Maximum clock frequency

A D flip-flop has $t_{pd} = 12\,\text{ns}$ and $t_{su} = 3\,\text{ns}$ . Find the maximum clock frequency.

Step 1: The minimum clock period must accommodate both propagation delay and setup time: $T_{min} = t_{pd} + t_{su}$ .
Step 2: Substitute values: $T_{min} = 12 + 3 = 15\,\text{ns}$ .
Step 3: Convert to frequency: $f_{max} = \frac{1}{15\,\text{ns}} = 66.7\,\text{MHz}$ .

The formula

f_{max} = 1 / (t_{pd} + t_{su})

applies when a single flip-flop feeds directly back to its own input (or to another flip-flop with no combinational logic in between).

Example 2: Pipeline timing

A two-stage pipeline has FF1 ( $t_{pd} = 8\,\text{ns}$ ) driving combinational logic ( $t_{comb} = 20\,\text{ns}$ ) that feeds FF2 ( $t_{su} = 5\,\text{ns}$ ). What is the maximum clock frequency?

T_{min} = t_{pd}(\text{FF1}) + t_{comb} + t_{su}(\text{FF2})

Figure 1. Pipeline timing path: data must traverse FF1 propagation delay, combinational logic delay, and arrive before FF2 setup window.

Step 1: Sum the path delays: $T_{min} = 8 + 20 + 5 = 33\,\text{ns}$ .
Step 2: Convert to frequency: $f_{max} = \frac{1}{33\,\text{ns}} \approx 30.3\,\text{MHz}$ .

The slowest path through combinational logic — the critical path — determines the maximum clock speed for the entire design.

Example 3: Identifying a setup violation

A flip-flop requires $t_{su} = 5\,\text{ns}$ . Data changes only 2 ns before the rising clock edge. Is the setup requirement met?

Figure 2. Data arrives too late: it changes 2 ns before the clock edge, but the flip-flop needs 5 ns of stability. The green arrow shows the required setup window — data violates it.

Step 1: The flip-flop needs data stable for $t_{su} = 5\,\text{ns}$ before the clock edge.
Step 2: Data only became stable 2 ns before the edge — that is 3 ns short of the requirement.
Step 3: This is a setup violation. The output may enter a metastable state and produce an unreliable result.

Always check that the data arrival time plus the setup requirement fits within one clock period. If it does not, either slow the clock or reduce the combinational logic delay.