Universal Gate Builder

Pick a target function (NOT, AND, OR, XOR, XNOR) and a family (NAND-only or NOR-only). Every combination is buildable, several in more than one way — compare gate count against levels of logic, toggle the inputs to trace live signals, and check the side-by-side truth table.

Universal gate

Build

2 NANDs2 levels of logic — the propagation delay

\overline{\overline{A \cdot B}} = A \cdot B

NAND already computes the inverse of AND. N2 is wired as an inverter and undoes that inversion.

Output:AND(A, B) = 0expected: 0✓ matches truth table

Truth table — AND from NAND

A	B	Built	Expected
0	0	0	0
0	1	0	0
1	0	0	0
1	1	1	1

Universal gates — NAND and NOR

A gate is universal if any Boolean function can be implemented using only that gate type. Both NAND and NOR are universal — AND, OR, and NOT can all be constructed from either one alone.

Building the basics from NAND

NOT: tie both inputs together — $\overline{A \cdot A} = \overline{A}$
AND: NAND followed by NOT — NAND(A,B) then invert
OR: invert both inputs then NAND — $A + B = \overline{\overline{A} \cdot \overline{B}}$ (De Morgan)

Why this matters in practice

Standard cell libraries in ASICs and FPGAs are often built primarily from NAND gates because they are fast and compact. Reducing a design to a single gate type also simplifies manufacturing: one photomask variant, one timing model.

Worked example — XOR from four NANDs

A two-input XOR ( $A \oplus B$ ) needs exactly four NAND gates. Let N1 = NAND(A, B). Then N2 = NAND(A, N1) and N3 = NAND(B, N1), and finally Y = NAND(N2, N3). Trace the truth table: when A = B the output is 0; when A ≠ B it is 1 — that is XOR. This four-gate pattern is the classic way FPGAs and standard-cell libraries synthesise XOR without a dedicated cell.

Common questions

Are AND, OR, or XOR universal too?: No. AND and OR can't produce inversion on their own, and XOR can't produce a constant 1 from a single variable — so none of them can build every function alone. Only NAND and NOR are universal single-gate sets.
NAND or NOR — which should I standardise on?: In CMOS, NAND is usually preferred: its series path uses fast NMOS transistors, giving it a speed and area edge over NOR (whose series PMOS stack is slower). NOR becomes attractive when a design is dominated by OR-heavy logic.

Learn more → Logic Gates — Learn

Quick experiments

Make an inverter out of one gate. Tie both NAND inputs to the same signal. The output is NOT A, because a NAND only reads 0 when every input is 1. The identical trick works on a NOR.
Build AND from two NANDs. First NAND gives NOT(A·B); feed that into a second NAND wired as an inverter. Two gates for an AND — which is exactly why chip libraries favour inverting logic.
Build OR from three NANDs. Invert A and invert B with one NAND each, then NAND the results. By De Morgan, NOT(NOT A · NOT B) = A + B.
Count the cost of XOR. XOR takes four NAND gates. Compare that against the two for AND — it is why XOR-heavy designs such as adders and parity trees dominate a chip's gate budget.
Do the same with NOR and compare. NOR is equally universal but the gate counts swap: OR becomes cheap and AND expensive. NAND wins in CMOS because series NMOS conducts better than series PMOS.

Formula reference

NAND: $Y = \overline{A \cdot B}$
Low only when every input is high.
NOR: $Y = \overline{A + B}$
High only when every input is low.
Inverter from a universal gate: $\overline{A \cdot A} = \bar{A} \qquad \overline{A + A} = \bar{A}$
Tie the inputs together.
OR from NAND, via De Morgan: $A + B = \overline{\bar{A} \cdot \bar{B}}$
Two inverters feeding a third NAND.

Symbol	Meaning	Unit
$\overline{A}$	Complement of A	—
$A \cdot B$	AND	—
$A + B$	OR	—

Common mistakes

Thinking NAND means NOT applied to each input.
The inversion is applied to the AND result, not the inputs. Inverting the inputs first gives NOT A · NOT B, which is NOR — a different function entirely.
Assuming a NAND-only design uses fewer gates.
Universality means it is possible, not cheaper. AND costs two NANDs and OR costs three. The win is manufacturing uniformity and speed per gate, not gate count.
Leaving unused inputs floating.
A floating CMOS input drifts and can switch randomly or oscillate. Tie unused NAND inputs high and unused NOR inputs low so they do not disturb the function.
Mixing NAND and NOR conversions in one step.
Convert the whole network to one gate type at a time. Applying De Morgan to some gates but not others leaves inversions unaccounted for and the circuit silently wrong.
Forgetting that each gate adds delay.
Building OR from three NANDs stacks two logic levels. In a critical path those extra propagation delays accumulate and can break timing.

Frequently asked questions

How many NAND gates does it take to make an XOR?

Four in the minimal form: one NAND makes a shared term that two more reuse, and a fourth combines them. A five-gate version also exists which inverts each input first, and is easier to read because it maps directly onto A AND NOT B, OR NOT A AND B.

Why does XOR need five NOR gates but only four NAND gates?

The four-gate topology is the same for both families, but with NOR gates it produces XNOR rather than XOR. Getting XOR from NOR therefore needs a fifth NOR wired as an inverter. The asymmetry runs the other way too: XNOR costs four NOR gates but five NAND gates.

How do you make a NOT gate from a NAND gate?

Tie both inputs to the same signal. A NAND only goes low when every input is high, so feeding it A twice gives NOT A. The same trick works with a NOR gate, which is why one gate type is enough to build everything.

Why are NAND and NOR called universal gates?

Any Boolean function can be built from NAND alone or NOR alone. Because each can produce NOT, AND and OR, and those three suffice for all logic, a single gate type can implement an entire design.

How do I make a NOT gate from a NAND gate?

Tie both NAND inputs to the same signal. NAND of A with A is NOT A, since the gate only outputs 0 when every input is 1. The same trick works with a NOR gate.

How do I build AND from NAND gates?

AND is NAND followed by an inverter, and that inverter is itself a NAND with its inputs tied together. So AND takes two NAND gates: the first produces NOT(A·B) and the second inverts it back.

Why do real chips prefer NAND over AND?

In CMOS a NAND gate needs four transistors, while AND needs those four plus two more for the inverter. NAND is also faster because it has one fewer stage, so libraries are built around inverting gates.

Is NAND or NOR better for building logic?

NAND is usually preferred in CMOS because series NMOS transistors conduct better than the series PMOS transistors a NOR gate requires, making NAND smaller and faster for the same drive strength.